DS3105 Maxim Integrated Products, DS3105 Datasheet - Page 2

• Manufacturer Part Number: DS3105
• Description: Line Card Timing IC
• Manufacturer: Maxim Integrated Products

1
2
3
4
5
6
7
STANDARDS COMPLIANCE ............................................................................................................................... 6
APPLICATION EXAMPLE..................................................................................................................................... 7
BLOCK DIAGRAM ................................................................................................................................................ 7
DETAILED DESCRIPTION ................................................................................................................................... 8
DETAILED FEATURES......................................................................................................................................... 9
PIN DESCRIPTIONS .......................................................................................................................................... 11
FUNCTIONAL DESCRIPTION............................................................................................................................ 15
7.1
7.2
7.3
7.4
7.5
7.6
7.7
Confidential. Document Issued Under Non-Disclosure Agreement. Confidential. Document Issued Under Non-Disclosure Agreement.
Overview.................................................................................................................................................... 15
Device Identification and Protection .......................................................................................................... 16
Local Oscillator and Master Clock Configuration ...................................................................................... 16
Input Clock Configuration .......................................................................................................................... 16
Input Clock Monitoring............................................................................................................................... 18
Input Clock Priority, Selection and Switching ............................................................................................ 20
DPLL Architecture and Configuration........................................................................................................ 22
7.4.1
7.4.2
7.5.1
7.5.2
7.5.3
7.6.1
7.6.2
7.6.3
7.6.4
7.6.5
7.6.6
7.7.1
7.7.2
7.7.3
7.7.4
7.7.5
7.7.6
7.7.7
7.7.8
7.7.9
7.7.10 Frequency and Phase Measurement ........................................................................................... 29
7.7.11 Input Jitter Tolerance.................................................................................................................... 30
7.7.12 Jitter Transfer ............................................................................................................................... 30
7.7.13 Output Jitter and Wander ............................................................................................................. 30
Signal Format Configuration......................................................................................................... 16
Frequency Configuration .............................................................................................................. 17
Frequency Monitoring................................................................................................................... 18
Activity Monitoring ........................................................................................................................ 18
Selected Reference Activity Monitoring........................................................................................ 19
Priority Configuration .................................................................................................................... 20
Automatic Selection Algorithm ..................................................................................................... 20
Forced Selection........................................................................................................................... 21
Ultra-Fast Reference Switching.................................................................................................... 21
External Reference Switching Mode ............................................................................................ 21
Output Clock Phase Continuity During Reference Switching....................................................... 21
T0 DPLL State Machine ............................................................................................................... 23
T4 DPLL State Machine ............................................................................................................... 26
Bandwidth..................................................................................................................................... 26
Damping Factor ............................................................................................................................ 26
Phase Detectors ........................................................................................................................... 26
Loss of Phase Lock Detection...................................................................................................... 27
Phase Build-Out ........................................................................................................................... 28
Input to Output (Manual) Phase Adjustment ................................................................................ 28
Phase Recalibration ..................................................................................................................... 28
Preliminary. Subject to Change Without Notice.
TABLE OF CONTENTS
2 of 110
DS3105