DS3105 Maxim Integrated Products, DS3105 Datasheet - Page 58

• Manufacturer Part Number: DS3105
• Description: Line Card Timing IC
• Manufacturer: Maxim Integrated Products

Register Name:
Register Description:
Register Address:
Name
Default
These registers are identical in function. ICRx is the control register for input clock ICx.
Bit 7: DIVN Mode (DIVN). When DIVN is set to 1 and LOCK8K=0, the input clock is divided down by a
programmable pre-divider. The resulting output clock is then passed to the DPLL. All input clocks for which DIVN=1
are divided by the factor specified in
FREQ field of that register must be set to the input frequency divided by the divide factor. When DIVN=1 and
LOCK8K=1 in an ICR register, the FREQ field of that register is decoded as the alternate frequencies. See sections
7.4.2.2
Bit 6: LOCK8K Mode (LOCK8K). When LOCK8K is set to 1 and DIVN=0, the input clock is divided down by a
preset pre-divider. The resulting output clock, which is always 8 kHz, is then passed to the DPLL. LOCK8K is
ignored when DIVN=0 and FREQ[3:0] = 1001 (2 kHz) or 1010 (4 kHz). When DIVN=1 and LOCK8K=1 in an ICR
register, the FREQ field of that register is decoded as the alternate frequencies. See sections
Bits 5 to 4: Leaky Bucket Configuration (BUCKET[1:0]). Each input clock has leaky bucket accumulator logic in
its activity monitor. The
Any of the four configurations can be specified for the input clock. See section 7.5.2.
Bits 3 to 0: Input Clock Frequency (FREQ[3:0]). When DIVN=0 and LOCK8K=0 (standard direct-lock mode),
this field specifies the input clock’s nominal frequency for direct-lock operation. When DIVN=0 and LOCK8K=1
(LOCK8K mode) this field specifies the input clock’s nominal frequency for LOCK8K operation. When DIVN=1 and
LOCK8K=0 (DIVN mode), this field specifies the frequency after the DIVN divider (i.e. input frequency divided by
DIVN
nominal frequency for direct-lock operation.
DIVN=0 or LOCK8K=0: (Standard direct-lock mode, LOCK8K mode, or DIVN mode)
Confidential. Document Issued Under Non-Disclosure Agreement. Confidential. Document Issued Under Non-Disclosure Agreement.
+ 1). When DIVN=1 and LOCK8K=1 (alternate direct-lock frequencies), this field specifies the input clock’s
and 7.4.2.4.
0 = Disabled
1 = Enabled
0 = Disabled
1 = Enabled
00 = leaky bucket configuration 0
01 = leaky bucket configuration 1
10 = leaky bucket configuration 2
11 = leaky bucket configuration 3
0000 = 8 kHz
0001 = 1544 or 2048 kHz (as determined by SONSDH bit in the
0010 = 6.48 MHz
0011 = 19.44 MHz
0100 = 25.92 MHz
0101 = 38.88 MHz
0110 = 51.84 MHz
0111 = 77.76 MHz
1000 = 155.52 MHz (only valid for LVDS inputs)
1001 = 2 kHz
1010 = 4 kHz
1011 = 6312 kHz
1100 = 5 MHz
1101 = 31.25 MHz (not a multiple of 8 kHz and therefore not valid for LOCK8K mode)
1110 to 1111 = undefined
DIVN
Bit 7
0
LBxy
LOCK8K
Bit 6
registers at addresses 50h to 5Fh specify four different leaky bucket configurations.
0
Input Configuration Register 3, 4, 5, 6, 9
22h, 23h, 24h, 25h, 28h
ICR3, ICR4, ICR5, ICR6, ICR9
Preliminary. Subject to Change Without Notice.
DIVN1
Bit 5
0
BUCKET[1:0]
and DIVN2. When DIVN=1 and LOCK8K=0 in an ICR register, the
58 of 110
Bit 4
0
Bit 3
MCR3
register)
Bit 2
FREQ[3:0]
see below
Bit 1
7.4.2.2
and
7.4.2.3
Bit 0
DS3105