DS3105 Maxim Integrated Products, DS3105 Datasheet - Page 11

• Manufacturer Part Number: DS3105
• Description: Line Card Timing IC
• Manufacturer: Maxim Integrated Products

6 PIN DESCRIPTIONS
Table 6-1. Input Clock Pin Descriptions
Table 6-2. Output Clock Pin Descriptions
Pin Name
REFCLK
IC3
IC4
IC5POS,
IC5NEG
IC6POS,
IC6NEG
IC9
SYNC1
SYNC2
SYNC3 / O3F0
Pin Name
OC3
OC6POS,
OC6NEG
FSYNC
MFSYNC
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(1)
(1)
Type
Type
O
I
I
I
I
DIFF
DIFF
I
I
I
I
O
O
O
DIFF
PD
PD
PD
PD
PD
PU
I
3
3
(2)
(2)
Pin Description
Reference Clock.
Connect to a 12.800 MHz, high-accuracy, high-stability, low-noise local oscillator (XO or
TCXO). See section 7.3.
Input Clock 3.
CMOS/TTL. Programmable frequency (default 8 kHz).
This input can be associated with the SYNC1 pin.
Input Clock 4.
CMOS/TTL. Programmable frequency (default 8 kHz).
This input can be associated with the SYNC2 pin.
Input Clock 5.
LVDS/LVPECL: see
CMOS/TTL: Bias IC5NEG to 1.4V and connect the single-ended signal to IC5POS.
This input can be associated with the SYNC1 pin.
Input Clock 6.
LVDS/LVPECL: see
CMOS/TTL: Bias IC6NEG to 1.4V and connect the single-ended signal to IC6POS.
This input can be associated with the SYNC2 pin.
Input Clock 9.
CMOS/TTL. Programmable frequency (default 19.44 MHz).
This input can be associated with the SYNC3 pin.
Frame Sync1 Input. 2 kHz, 4 kHz or 8 kHz.
FSCR3:SOURCE != 11XX
FSCR3:SOURCE = 11XX
Frame Sync2 Input. 2 kHz, 4 kHz or 8 kHz.
FSCR3:SOURCE != 11XX
FSCR3:SOURCE = 11XX
Frame Sync3 Input. 2 kHz, 4 kHz or 8 kHz. / OC3 Frequency Select 0.
This pin is sampled when the RST pin goes high and the value is used as O3F0 which together
with O3F2 and O3F1 sets the default frequency of the OC3 output clock pin. See
After RST goes high this pin becomes the SYNC3 input pin (2, 4 or 8 kHz) associated with IC9.
It is only used as SYNC3 when FSCR2.SOURCE = 11XX.
Pin Description
Output Clock 3.
CMOS/TTL. Programmable frequency. Default frequency selected by O3F[2:0] pins when the
RST pin goes high, 19.44 MHz if O3F[2:0] pins left open). See
Output Clock 6.
LVDS/LVPECL. Programmable frequency. Default frequency selected by O6F[2:0] pins when
the RST pin goes high, 38.88 MHz if O6F[2:0] pins left open). The output mode is selected by
MCR8.OC6SF[1:0]. See
8 kHz FSYNC.
CMOS/TTL. 8 kHz frame sync or clock. (default 50% duty cycle clock, non-inverted) The pulse
polarity and width are selectable using FSCR1.8KINV and FSCR1.8KPUL.
2 kHz MFSYNC.
CMOS/TTL. 2 kHz frame sync or clock. (default 50% duty cycle clock, non-inverted) The pulse
polarity and width are selectable using FSCR1.2KINV and FSCR1.2KPUL.
LVDS/LVPECL or CMOS/TTL. Programmable frequency (default 19.44 MHz).
LVDS/LVPECL or CMOS/TTL. Programmable frequency (default 19.44 MHz).
This pin is the external frame sync input associated with any input pin using the
FSCR3:SOURCE field.
This pin is the external frame sync signal associated with IC3 or IC5 depending on
which one is currently selected and the setting of FSCR1.SYNCSRC[1:0].
This pin is not used for the external frame sync signal.
This pin is the external frame sync signal associated with IC4 or IC6 depending on
which one is currently selected and the setting of FSCR1.SYNCSRC[1:0].
Preliminary. Subject to Change Without Notice.
Table
Table
Table
10-4,
10-4,
11 of 110
10-5,
Figure 10-1
Figure 10-1
Table 10-6
and
and
,
Figure
Figure
Figure 10-1
10-2.
10-2.
and
Table
Figure 10-3.
7-18.
Table
7-18.
DS3105