DS3105 Maxim Integrated Products, DS3105 Datasheet - Page 109

• Manufacturer Part Number: DS3105
• Description: Line Card Timing IC
• Manufacturer: Maxim Integrated Products

14 DATA SHEET REVISION HISTORY
REVISION
02/28/07
Confidential. Document Issued Under Non-Disclosure Agreement. Confidential. Document Issued Under Non-Disclosure Agreement.
4/17/07
4/30/07
5/10/07
5/18/07
3/1/07
3/5/07
3/9/07
4/3/07
4/4/07
First version released to customers.
In the
LOCK8K mode and to indicate that 31.25 MHz is not a valid setting for LOCK8K mode.
Updated section
whichever is smaller.
In
In section
Added Note 2 to
Added Note 2 to
Updated
input clocks.
Deleted V
1-1.
Added section 7.13.
Deleted mention of slave mode from MCR9:AUTOBW bit description.
In the
In the
value for bit 6 to 0.
Edited section
DPLL’s hard limit is fixed at ±80ppm and is not controlled by the HARDLIM field.
In
typical.
Added information about custom clock rates to page 1 bullets and section
a new section 7.8.2.6.
Changed caption for
In section 7.5.3, second paragraph, first sentence, deleted “frequency range error” as a criteria
for entering mini holdover.
Changed pin name INTREQ/SRFAIL to INTREQ/LOS and changed register bit
INTCR:SRFAIL to LOS. This affected the pin description in
in
Edited
Updated the data sheet in several places to indicate CMOS/TTL input clock pins can accept
any multiple of 2kHz up to 125MHz and that differential inputs clock pins can accept any
multiple of 2kHz up to 131.072MHz, any multiple of 8kHz up to 155.52MHz plus 156.25MHz.
In
In the
In the
Updated page 1 feature bullet, section
maximum custom frequency is 311.04MHz.
In
OCnINV to 8KINV and 2KINV, and OCnPOL to 8KPOL and 2KPOL.
In
through OC5B when VDDIOB is 2.5V.
In
Table
Table 7-1
Table 10-6
Table
Figure
Table
Table
ICR
OPSTATE
MCR4
T0LBW
T0ABW
T4BW
8-1, the MSR2:SRFAIL register description, and the bit descriptions for INTCR.
7-9, added frequencies 45.824, 22.912, 29.824 and 14.912 MHz.
10-3, changed max from VDD to VDDIO and added separate V
10-10, changed t
Table 10-7
7-1, changed OC10 to FSYNC, OC11 to MFSYNC, OCnEN to FSEN and MFSEN,
HYST
7.8.1
register description, updated the FREQ field description explicitly mention its use in
added indications that IC5 and IC6 can be configured as CMOS/TTL inputs.
register description, deleted the T4DIGFB bit description and changed the default
deleted VOHPECL and VOLPECL specs and changed VOSPECL spec to 0.8V
register to not have bit 2.
spec from
register definition, changed the default value to 00h.
register definition, changed the default value to 01h.
7.7.6
added hyperlink to Maxim app note HFAN-1.0.
7.4
Table
Table
register description, changed the default value of T4LOCK to 0.
Preliminary. Subject to Change Without Notice.
and the
to clarify minimum high time and low time (and therefore duty cycle) for
to indicate minimum high time or low time is 3ns or 30% of clock period,
Table 7-14
10-5.
10-6.
Table 10-4
DV
max to 50ns.
DLIMIT1
from “Possible Frequencies” to “Standard Frequencies”.
109 of 110
and deleted reference to IEEE1596.3 standard from
and DLIMIT3:FLLOL descriptions to indicate that the T4
5
DESCRIPTION
feature bullet and section
Table
6-3, the name of
7.8.2.6
OH
5
text to indicate
spec for OC1B
bullets, and added
INTCR
DS3105
Table
bit 3