DS3105 Maxim Integrated Products, DS3105 Datasheet - Page 50

• Manufacturer Part Number: DS3105
• Description: Line Card Timing IC
• Manufacturer: Maxim Integrated Products

Register Name:
Register Description:
Register Address:
Name
Default
Bits 5 to 2: Input Clock Status Change (IC6 to IC3). Each of these latched status bits is set to 1 when the
corresponding
set again until the
interrupt request on the INTREQ pin if the corresponding interrupt enable bit is set in the
7.5
Register Name:
Register Description:
Register Address:
Name
Default
Bit 7: T0 DPLL State Change (STATE). This latched status bit is set to 1 when the operating state of the T0 DPLL
changes. STATE is cleared when written with a 1 and not set again until the operating state changes again. When
STATE is set it can cause an interrupt request on the INTREQ pin if the STATE interrupt enable bit is set in the
IER2
section 7.7.1.
Bit 6: Selected Reference Failed (SRFAIL). This latched status bit is set to 1 when the selected reference to the
T0 DPLL fails, (i.e. no clock edges in two UI). SRFAIL is cleared when written with a 1. When SRFAIL is set it can
cause an interrupt request on the INTREQ pin if the SRFAIL interrupt enable bit is set in the
is not set in Free-run mode or Holdover mode. See section 7.5.3.
Bit 0: Input Clock Status Change (IC9). This latched status bit is set to 1 when the corresponding
bit changes state (set or cleared). Each bit is cleared when written with a 1 and not set again until the
changes state again. When this latched status bit is set it can cause an interrupt request on the INTREQ pin if the
corresponding interrupt enable bit is set in the
criteria.
Register Name:
Register Description:
Register Address:
Name
Default
Bits 2 to 0: Current DPLL Frequency (FREQ[18:16]). See the
for input clock validation/invalidation criteria.
Confidential. Document Issued Under Non-Disclosure Agreement. Confidential. Document Issued Under Non-Disclosure Agreement.
register. The current operating state can be read from the T0STATE field of the
VALSR1
STATE
Bit 7
Bit 7
Bit 7
--
0
--
1
0
VALSR1
status bit changes state (set or cleared). Each bit is cleared when written with a 1 and not
SRFAIL
bit changes state again. When one of these latched status bits is set it can cause an
Bit 6
Bit 6
Bit 6
--
--
0
0
0
MSR1
Master Status Register 1
05h
MSR2
Master Status Register 2
06h
FREQ3
Frequency Register 3
07h
Preliminary. Subject to Change Without Notice.
Bit 5
Bit 5
Bit 5
IC6
--
--
1
0
0
IER2
50 of 110
register. See section
Bit 4
Bit 4
Bit 4
IC5
--
--
1
0
0
FREQ1
Bit 3
Bit 3
Bit 3
IC4
--
1
--
0
0
register description.
7.5
for input clock validation/invalidation
Bit 2
Bit 2
Bit 2
IC3
1
--
0
0
FREQ[18:16]
IER1
OPSTATE
IER2
Bit 1
Bit 1
Bit 1
register. See section
--
--
1
0
0
register. SRFAIL
VALSR
register. See
VALSR2
Bit 0
Bit 0
Bit 0
DS3105
IC9
--
1
1
0
status
bit