DS3105 Maxim Integrated Products, DS3105 Datasheet - Page 75

• Manufacturer Part Number: DS3105
• Description: Line Card Timing IC
• Manufacturer: Maxim Integrated Products

Register Name:
Register Description:
Register Address:
Name
Default
Bits 3 to 0: Output Frequency of OC3 (OFREQ3[3:0]). This field specifies the frequency of output clock OC3.
The frequencies of the T0 APLL and T4 APLL are configured in the
Digital2 frequencies are configured in the
O3F[2:0] bits, see
AOF3=0: (standard decodes)
AOF3=1: (alternate decodes)
Confidential. Document Issued Under Non-Disclosure Agreement. Confidential. Document Issued Under Non-Disclosure Agreement.
0000 = Output disabled (i.e. low)
0001 = 2 kHz
0010 = 8 kHz
0011 = Digital2 (see
0100 = Digital1 (see
0101 = T0 APLL frequency divided by 48
0110 = T0 APLL frequency divided by 16
0111 = T0 APLL frequency divided by 12
1000 = T0 APLL frequency divided by 8
1001 = T0 APLL frequency divided by 6
1010 = T0 APLL frequency divided by 4
1011 = T4 APLL frequency divided by 64
1100 = T4 APLL frequency divided by 48
1101 = T4 APLL frequency divided by 16
1110 = T4 APLL frequency divided by 8
1111 = T4 APLL frequency divided by 4
0000 = Output disabled (i.e. low)
0001 = T0 APLL frequency divided by 64
0010 = T4 APLL frequency divided by 20
0011 = T4 APLL frequency divided by 12
0100 = T4 APLL frequency divided by 10
0101 = T4 APLL frequency divided by 5
0110 = T4 APLL frequency divided by 2
0111 = T4 selected reference (after dividing)
1000 to 1111 = undefined
Bit 7
Table
0
0
7-18. The decode of this field is controlled by the value of the OCR5.AOF3 bit.
Table
Table
Bit 6
0
0
OCR2
Output Configuration Register 2
61h
7-8)
7-7)
Preliminary. Subject to Change Without Notice.
MCR7
Bit 5
0
0
register. See section 7.8.2.3. The default frequency is set by the
75 of 110
Bit 4
0
0
Bit 3
T0CR1
and
Bit 2
T4CR1
OFREQ3[3:0]
see below
registers. The Digital1 and
Bit 1
Bit 0
DS3105