DS3105 Maxim Integrated Products, DS3105 Datasheet - Page 100

• Manufacturer Part Number: DS3105
• Description: Line Card Timing IC
• Manufacturer: Maxim Integrated Products

10.2 Input Clock Timing
Table 10-7. Input Clock Timing
(VDD = 1.8V ± 10%; VDDIO = 3.3V ± 5%, T
10.3 Output Clock Timing
Table 10-8. Input Clock to Output Clock Delay
Table 10-9. Output Clock Phase Alignment, Frame Sync Alignment Mode
See section
Input Clock Period,
CMOS/TTL Input Pins
Input Clock Period,
LVDS/LVPECL Input Pins
Input Clock High, Low Time
8 kHz (FSYNC)
2 kHz
8 kHz
1.544 MHz
2.048 MHz
44.736 MHz
34.368 MHz
6.48 MHz
19.44 MHz
25.92 MHz
38.88 MHz
51.84 MHz
77.76 MHz
155.52 MHz
311.04 MHz
OUTPUT FREQUENCY
FREQUENCY
155.52 MHz
Confidential. Document Issued Under Non-Disclosure Agreement. Confidential. Document Issued Under Non-Disclosure Agreement.
19.44 MHz
25.92 MHz
38.88 MHz
51.84 MHz
77.76 MHz
6.48 MHz
INPUT
8 kHz
PARAMETER
7.9
for details on frame sync alignment and the SYNC1,2,3 pins.
FREQUENCY
155.52 MHz
19.44 MHz
25.92 MHz
38.88 MHz
51.84 MHz
77.76 MHz
6.48 MHz
OUTPUT
8 kHz
OUTPUT CLOCK FALLING EDGE
DELAY, MFSYNC FALLING
SYMBOL
t
t
t
H
CYC
CYC
Preliminary. Subject to Change Without Notice.
, t
L
-2.0 ± 1.25ns
-2.0 ± 1.25ns
-2.0 ± 1.25ns
-2.0 ± 1.25ns
-2.0 ± 1.25ns
-2.0 ± 1.25ns
-2.0 ± 1.25ns
-2.0 ± 1.25ns
-2.0 ± 1.25ns
-2.0 ± 1.25ns
0.0 ± 1.25ns
0.0 ± 1.25ns
0.0 ± 0.5ns
0.0 ± 0.5ns
0.0 ± 0.5ns
EDGE TO
A
CLOCK EDGE TO
= -40°C to +85°C)
OUTPUT CLOCK
DELAY, INPUT
0.0 ± 1.5ns
-12 ± 1.5ns
0.0 ± 1.5ns
0.0 ± 1.5ns
0.0 ± 1.5ns
0.0 ± 1.5ns
0.0 ± 1.5ns
0.0 ± 1.5ns
whichever is smaller
6.4ns (156.25MHz)
3ns or 30% of t
EDGE
100 of 110
8ns (125MHz)
MIN
CYC
,
TYP
500μs (2kHz)
500μs (2kHz)
MAX
DS3105