DS3105 Maxim Integrated Products, DS3105 Datasheet - Page 26

• Manufacturer Part Number: DS3105
• Description: Line Card Timing IC
• Manufacturer: Maxim Integrated Products

MCLK offset specified in the MCLKFREQ field in registers
MCR3.FRUNHO is set the HOCR3:AVG bit is ignored.
7.7.1.7
When the selected reference fails, the fast activity monitor (section 7.5.3) isolates the T0 DPLL from the reference
within one or two clock cycles to avoid adverse effects on the DPLL frequency. When this fast isolation occurs, the
DPLL enters a temporary mini-holdover mode, with a frequency equal to an instantaneous value 50 to 100 ms old
from the integral path of the loop filter. Mini-holdover lasts until the selected reference becomes active or the state
machine enters the holdover state. If the free-run holdover mode is set (FRUNHO=1 in MCR3), the mini-holdover
frequency accuracy is exactly the same as the external oscillator accuracy plus the offset set by the MCLKFREQ
field in registers
7.7.2 T4 DPLL State Machine
The T4 DPLL state machine is simpler than the T0 state machine. The T4 DPLL does not generate any output
clock signals but it can be used to measure phase between two inputs and it can lock to an input to measure the
frequency and possibly stability of the input.
7.7.3
The bandwidth of the T4 DPLL is configured in the
The bandwidth of the T0 DPLL is configured in the
400 Hz. The AUTOBW bit in the
DPLL uses the T0ABW bandwidth during acquisition (not phase locked) and the T0LBW bandwidth when phase
locked. When AUTOBW=0 the T0 DPLL uses the T0LBW bandwidth all the time, both during acquisition and when
phase locked.
When LIMINT=1 in the
minimum or maximum frequency. Setting LIMINT=1 minimizes overshoot when the DPLL is pulling in.
7.7.4
The damping factor for the T0 DPLL is configured in the DAMP field of the
factor of the T4 DPLL is configured in the DAMP field of the
both DPLLs are chosen to give a maximum jitter/wander gain peak of approximately 0.1 dB. Available settings are
a function of DPLL bandwidth (configured in the T4BW,
Table 7-4. Damping Factors and Peak Jitter/Wander Gain
7.7.5 Phase Detectors
Phase detectors are used to compare a PLL’s feedback clock with its input clock. Several phase detectors are
available in the T0 and T4 DPLLs:
Bandwidth
18 Hz
35 Hz
70 to 400 Hz
Confidential. Document Issued Under Non-Disclosure Agreement. Confidential. Document Issued Under Non-Disclosure Agreement.
Bandwidth
Damping Factor
•
•
•
Mini-Holdover
Phase/frequency detector (PFD)
Early/late phase detector (PD2) for fine resolution
Multi-cycle phase detector (MCPD) for large input jitter tolerance and/or faster lock times
MCLK1
1
2
3, 4, 5
1
2
3
4, 5
1
2
3
4
5
DAMP[2:0]
Value
and
MCR9
MCLK2
register, the DPLL’s integral path is limited (i.e. frozen) when the DPLL reaches
MCR9
Preliminary. Subject to Change Without Notice.
(see section 7.3).
Damping
register controls automatic bandwidth selection. When AUTOBW=1, the T0
Factor
10
10
20
1.2
2.5
5
1.2
2.5
5
1.2
2.5
5
T4BW
T0ABW
26 of 110
Gain Peak, dB
T0ABW
register to be 18 Hz to 70 Hz.
and
0.4
0.2
0.1
0.4
0.2
0.1
0.06
0.4
0.2
0.1
0.06
0.03
T4CR2
and
MCLK1
T0LBW
T0LBW
register. The reset default damping factors for
registers for various values from 18 Hz to
and
registers). See
MCLK2
T0CR2
register, while the damping
(see section 7.3). When
Table
7-4.
DS3105