DS3105 Maxim Integrated Products, DS3105 Datasheet - Page 71

• Manufacturer Part Number: DS3105
• Description: Line Card Timing IC
• Manufacturer: Maxim Integrated Products

Register Name:
Register Description:
Register Address:
Name
Default
Bit 6: SRFAIL Pin Enable (SRFPIN). When this bit is set to 1, the SRFAIL pin is enabled. When enabled the
SRFAIL pin follows the state of the SRFAIL status bit in the
indication of the failure of the current reference. See section 7.5.3.
Bit 5: Ultra-Fast Switching Mode (UFSW). See section 7.6.4.
Bit 4: External Reference Switching Mode (EXTSW). This bit enables external reference switching mode. In this
mode, if the SRCSW pin is high the T0 DPLL is forced to lock to input IC3 (if the priority of IC3 is non-zero) or IC5
(if the priority of IC3 is zero) whether or not the selected input has a valid reference signal. If the SRCSW pin is low
the device is forced to lock to input IC4 (if the priority of IC4 is non-zero) or IC6 (if the priority of IC4 is zero)
whether or not the selected input has a valid reference signal. During reset the default value of this bit is latched
from the SRCSW pin. This mode only controls the T0 DPLL. The T4 DPLL is not affected. See section 7.6.5.
Bit 3: Phase Build-Out Freeze (PBOFRZ). This bit freezes the current input-output phase relationship and does
not allow further phase build-out events to occur. This bit affects phase build-out in response to reference switching
(section 7.7.7.1).
Bit 2: Phase Build-Out Enable (PBOEN). When this bit is set to 1 a phase build-out event occurs every time the
T0 DPLL changes to a new reference, including exiting the Holdover and Free-run states. When this bit is set to 0,
the T0 DPLL locks to the new source with zero degrees of phase difference. See section 7.7.7.
Register Name:
Register Description:
Register Address:
Name
Default
Bit 4: T4 or T0 Path Select (T4T0). This bit specifies which path is being accessed when reads or writes are
made to the following registers: PTAB1, PTAB2, FREQ1, FREQ2, FREQ3, IPR2, IPR3, IPR5,
PHASE2.
Confidential. Document Issued Under Non-Disclosure Agreement. Confidential. Document Issued Under Non-Disclosure Agreement.
0 = SRFAIL pin disabled (not driven)
1 = SRFAIL pin enabled
0 = Disabled
1 = Enabled. The current reference source is disqualified after less than three missing clock cycles.
0 = Normal operation
1 = External switching mode
0 = Not frozen
1 = Frozen
0 = T0 path
1 = T4 path
Bit 7
Bit 7
--
--
1
0
SRFPIN
Bit 6
Bit 6
--
0
0
MCR10
Master Configuration Register 10
48h
MCR11
Master Configuration Register 11
4Bh
Preliminary. Subject to Change Without Notice.
UFSW
Bit 5
Bit 5
--
0
0
see below
EXTSW
71 of 110
T4T0
Bit 4
Bit 4
0
MSR2
PBOFRZ
Bit 3
Bit 3
0
--
0
register. This gives the system a very fast
PBOEN
Bit 2
Bit 2
--
1
0
Bit 1
Bit 1
--
--
0
0
PHASE1
Bit 0
Bit 0
DS3105
--
--
0
0
and