DS3105 Maxim Integrated Products, DS3105 Datasheet - Page 78

• Manufacturer Part Number: DS3105
• Description: Line Card Timing IC
• Manufacturer: Maxim Integrated Products

Register Name:
Register Description:
Register Address:
Name
Default
Bit 7: T4 Measure T0 Phase (T4MT0). When this bit is set to 1 the T4 phase detector is configured to measure the
phase difference between the selected T0 DPLL input clock and the selected the T4 DPLL input clock. See section
7.7.10.
Bit 6: T4 APLL Source from T0 (T4APT0). When this bit is set to 0, T4CR1:T4FREQ configures the T4 APLL DFS
frequency. The T4 APLL DFS frequency affects the frequency of the T4 APLL which in turn affects the available
output frequencies on the output clock pins (see the
APLL DFS is configured by the T0CR1:T0FT4[2:0] field below. See section 7.8.2.
Bits 5 to 3: T0 Frequency to T4 APLL (T0FT4[2:0]). When the T4APT0 bit is set to 1, this field specifies the
frequency of the T4 APLL DFS. This frequency can be different than the frequency specified by T0CR1:T0FREQ.
See section 7.8.2.
Bits 2 to 0: T0 DPLL Output Frequency (T0FREQ[2:0]). This field configures the T0 APLL DFS frequency. The
T0 APLL DFS frequency affects the frequency of the T0 APLL, which in turn affects the available output
frequencies on the output clock pins (see the registers). See section
the O6F[2:0] and O3F[2:0] pins as described in
Confidential. Document Issued Under Non-Disclosure Agreement. Confidential. Document Issued Under Non-Disclosure Agreement.
0 = T4 can lock to an input to measure frequency
1 = Enable T4-measure-T0-phase mode
0 = T4 APLL frequency is determined by T4FREQ
1 = T4 APLL frequency is determined by T0FT4
T0FT4
000 =
001 =
010 =
011 =
100 =
101 =
110 =
111 =
T0FREQ
000 =
001 =
010 =
011 =
100 =
101 =
110 =
111 =
T4MT0
Bit 7
0
T4 APLL DFS Frequency
24.576 MHz (12 x E1)
62.500 MHz (GbE ÷ 16)
32.768 MHz (16 x E1)
{unused value}
37.056 MHz (24 x DS1)
{unused value}
24.704 MHz (16 x DS1)
25.248 MHz (4 x 6312 kHz)
T0 APLL DFS Frequency
77.76 MHz
77.76 MHz
24.576 MHz (12 x E1)
32.768 MHz (16 x E1)
37.056 MHz (24 x DS1)
24.704 MHz (16 x DS1)
25.248 MHz (4 x 6312 kHz)
62.500 MHz (GbE ÷ 16)
T4APT0
Bit 6
0
T0CR1
T0 DPLL Configuration Register 1
65h
Preliminary. Subject to Change Without Notice.
Bit 5
0
Table
T4 APLL Frequency (4 x T4 APLL DFS)
98.304 MHz (48 x E1)
250.000 MHz (GbE ÷ 4)
131.072 MHz (64 x E1)
{unused value}
148.224 MHz (96 x DS1)
{unused value}
98.816 MHz (64 x DS1)
100.992 MHz (16 x 6312 kHz)
T0FT4[2:0]
T0 APLL Frequency (4 x T0 APLL DFS)
311.04 MHz (4 x 77.76 MHz)
311.04 MHz (4 x 77.76 MHz)
98.304 MHz (48 x E1)
131.072 MHz (64 x E1)
148.224 MHz (96 x DS1)
98.816 MHz (64 x DS1)
100.992 MHz (16 x 6312 kHz)
250.000 MHz (GbE ÷ 4)
78 of 110
9
7-15.
Bit 4
registers). When this bit is set to 1, the frequency of the T4
0
Bit 3
0
7.8.2.
The default frequency is controlled by
Bit 2
T0FREQ[2:0]
see below
Bit 1
Bit 0
DS3105