DS3105 Maxim Integrated Products, DS3105 Datasheet - Page 31

• Manufacturer Part Number: DS3105
• Description: Line Card Timing IC
• Manufacturer: Maxim Integrated Products

7.8 Output Clock Configuration
A total of 4 output clock pins, OC3, OC6, FSYNC and MFSYNC are available on the device. Output clocks OC3
and OC6 are individually configurable for a variety of frequencies. Output clocks FSYNC and MFSYNC are more
specialized, serving as an 8 KHz frame sync (FSYNC), and a 2 KHz multi-frame sync (MFSYNC).
provides more detail on the capabilities of the output clock pins.
Table 7-6. Output Clock Capabilities
7.8.1 Signal Format Configuration
Output clock OC6 is an LVDS compatible, LVPECL level-compatible output. The type of output can be selected or
the output can be disabled using the OC6SF configuration bits in the
mode generates a differential signal that is large enough for most LVPECL receivers. Some LVPECL receivers
have a limited common mode signal range which can be accommodated for by using an AC coupled signal. The
LVDS electrical specifications are listed in
10-1. The LVPECL level-compatible electrical specifications are listed in
LVPECL receiver termination is shown in
LVPECL and CML inputs on neighboring ICs using a few external passive components. See
HFAN-1.0
Output clocks OC3, FSYNC, and MFSYNC are CMOS/TTL signal format.
7.8.2
The frequency of output clocks OC3 and OC6 is a function of the settings used to configure the components of the
T0 PLL paths. These components are shown in the detailed block diagram of
The DS3105 uses digital frequency synthesis (DFS) to generate various clocks. In DFS a high-speed master clock
(204.8 MHz) is divided down to the desired output frequency by adding a number to an accumulator. The DFS
output is a coding of the clock output phase which is used by a special circuit to determine where to put the edges
of the output clock between the clock edges of the master clock. The edges of the output clock, however, are not
ideally located in time resulting in jitter with an amplitude typically less than 1 nsec pk-pk.
7.8.2.1
See
synthesize internal clocks from which the output and feedback clocks are derived. The T4 DPLL only has a single
DFS feedback clock, whereas there are two DFS output clock signals in the T0 DPLL, one for the output clocks and
one for the feedback clock.
In the T0 DPLL the feedback clock signal output handles phase build-out or any phase offset configured in the
OFFSET
may have a phase offset. The T0 and T4 feedback DFS blocks are always connected to the T0 forward DFS and
the T4 forward DFS, respectively. The feedback DFS blocks synthesize the appropriate locking frequencies for use
by the phase-frequency detectors (PFDs). See section 7.4.2.
7.8.2.2
See
blocks and three APLL DFS blocks. The T0 APLL, the T0 APLL2 and the T4 APLL (and their output dividers) get
their frequency references from three associated APLL DFS blocks. All of the output DFS blocks are connected to
the T0 DPLL..
The 2K8K DFS and FSYNC DFS blocks generate both 2 kHz and 8 kHz signals which have about 1 ns pk-pk jitter.
The FSYNC (8 kHz) and MFSYNC(2 kHz) signals come from the FSYNC DFS block, which is always connected to
the T0 DPLL when not in independent mode (FSCR2:INDEP=1). In independent mode they will be frequency
locked, but not phase aligned with the OC3 and OC6 outputs. The 2kHz and 8 kHz signals that can be output on
OC3 or OC6 always come from the 2K8K DFS, which is always connected to the T0 DPLL..
Output Clock
OC3
OC6
OC10
OC11
Confidential. Document Issued Under Non-Disclosure Agreement. Confidential. Document Issued Under Non-Disclosure Agreement.
Figure
Figure
Frequency Configuration
registers. Thus the T0 DPLL output clock signals and the feedback clock signal are frequency locked but
T0 and T4 DPLL Details
Output DFS and APLL Details
for details.
7-1. The T0 and T4 forward DFS blocks use the 204.8 MHz master clock and DFS technology to
7-1. The output clock frequencies are determined by two 2kHz/8kHz DFS blocks, two DIG12 DFS
Signal Format
CMOS/TTL
LVDS/PECL
CMOS/TTL
Preliminary. Subject to Change Without Notice.
Frequencies Supported
Frequency selection per section
Table
8 KHz frame sync with programmable pulse width and polarity
2 KHz multiframe sync with programmable pulse width and polarity
Figure
Table
7-13
10-5, and the recommended LVDS termination is shown in
10-3. These differential outputs can be easily interfaced to LVDS,
31 of 110
MCR8
7.8.2.3
register. The LVPECL level-compatible
Figure
and
Table
Table 7-7
7-1.
10-6, and the recommended
through
Maxim App Note
Table 7-6
DS3105
Figure