DS3105 Maxim Integrated Products, DS3105 Datasheet - Page 56

• Manufacturer Part Number: DS3105
• Description: Line Card Timing IC
• Manufacturer: Maxim Integrated Products

Register Name:
Register Description:
Register Address:
Name
Default
This register has the same behavior as the and
Register Name:
Register Description:
Register Address:
Name
Default
This register has the same behavior as the
Register Name:
Register Description:
Register Address:
Name
Default
Bit 6: Holdover Frequency Ready (HORDY). This latched status bit is set to 1 when the T0 DPLL has a holdover
value that has been averaged over the 1-second holdover averaging period. HORDY is cleared when written with a
1. When HORDY is set it can cause an interrupt request on the INTREQ pin if the HORDY interrupt enable bit is
set in the
Bit 5: Multi-Register Access Aborted (MRAA). This latched status bit is set to 1 when a multi-byte access (read
or write) is interrupted by another access to the device. MRAA is cleared when written with a 1. MRAA cannot
cause an interrupt to occur. See section 8.3.
Confidential. Document Issued Under Non-Disclosure Agreement. Confidential. Document Issued Under Non-Disclosure Agreement.
IER4
register. See section 7.7.1.6.
Bit 7
Bit 7
Bit 7
--
--
--
0
0
0
HORDY
Bit 6
Bit 6
Bit 6
--
--
0
0
0
ISR3
Input Status Register 3
12h
ISR5
Input Status Register 5
14h
MSR4
Master Status Register 4
17h
Preliminary. Subject to Change Without Notice.
MRAA
ACT6
Bit 5
Bit 5
Bit 5
ISR2
--
1
0
0
ISR2
register, but for input clock IC9.
56 of 110
LOCK6
registers, but for input clocks IC5 and IC6.
Bit 4
Bit 4
Bit 4
--
--
0
0
0
Bit 3
Bit 3
Bit 3
--
--
0
0
--
0
Bit 2
Bit 2
Bit 2
--
--
--
0
0
0
ACT5
ACT9
Bit 1
Bit 1
Bit 1
--
1
1
0
LOCK5
LOCK9
Bit 0
Bit 0
Bit 0
DS3105
--
0
0
0