DS3105 Maxim Integrated Products, DS3105 Datasheet - Page 72

• Manufacturer Part Number: DS3105
• Description: Line Card Timing IC
• Manufacturer: Maxim Integrated Products

Register Name:
Register Description:
Register Address:
Name
Default
Bit 7: Frequency Limit Loss of Lock (FLLOL). When this bit is set to 1, the T0 DPLL and the T4 DPLL internally
declare loss-of-lock when their hard limits are reached. The T0 DPLL hard frequency limit is set in the
HARDLIM[9:0] field in the
See section 7.7.6.
Bits 6 to 0: DPLL Soft Frequency Limit (SOFTLIM6:0]). This field is an unsigned integer that specifies the soft
frequency limit for the T0 DPLL and the T4 DPLL. The soft limit is only used for monitoring; exceeding this limit
does not cause loss-of-lock. The limit in ppm is ±SOFTLIM[6:0] * 0.628. The default value is ±8.79 ppm. When the
T0 DPLL frequency reaches the soft limit the T0SOFT status bit is set in the
DPLL frequency reaches the soft limit the T4SOFT status bit is set in OPSTATE. See section 7.7.6.
Register Name:
Register Description:
Register Address:
Name
Default
Bit 6: Interrupt Enable for Holdover Frequency Ready (HORDY). This bit is an interrupt enable for the HORDY
bit in the
Register Name:
Register Description:
Register Address:
Name
Default
Bit 5: Alternate Output Frequency Mode Select 6 (AOF6). This bit controls the decoding of the OCR3.OFREQ6
field for the OC6 pin.
Bit 2: Alternate Output Frequency Mode Select 3 (AOF3). This bit controls the decoding of the OCR2.OFREQ3
field for the OC3 pin.
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0 = DPLL declares loss-of-lock normally
1 = DPLL also declares loss-of-lock when the hard frequency limit is reached
0 = Mask the interrupt
1 = Enable the interrupt
0 = Standard decodes
1 = Alternate decodes
0 = Standard decodes
1 = Alternate decodes
MSR4
FLLOL
register.
Bit 7
Bit 7
Bit 7
--
--
1
0
0
DLIMIT1
HORDY
Bit 6
Bit 6
Bit 6
--
0
0
0
DLIMIT3
DPLL Frequency Limit Register 3
4Dh
IER4
Interrupt Enable Register 4
4Eh
OCR5
Output Configuration Register 1
4Fh
and
Preliminary. Subject to Change Without Notice.
DLIMIT2
AOF6
Bit 5
Bit 5
Bit 5
--
0
0
0
registers. The T4 DPLL hard frequency limit is fixed at ±80ppm.
72 of 110
Bit 4
Bit 4
Bit 4
--
--
0
0
0
SOFTLIM[6:0]
Bit 3
Bit 3
Bit 3
1
--
0
--
0
AOF3
Bit 2
Bit 2
Bit 2
OPSTATE
--
1
0
0
register. When the T4
Bit 1
Bit 1
Bit 1
--
1
0
--
0
Bit 0
Bit 0
Bit 0
DS3105
--
--
0
0
0