DS3105 Maxim Integrated Products, DS3105 Datasheet - Page 76

• Manufacturer Part Number: DS3105
• Description: Line Card Timing IC
• Manufacturer: Maxim Integrated Products

Register Name:
Register Description:
Register Address:
Name
Default
Bits 7 to 4: Output Frequency of OC6 (OFREQ6[3:0]). This field specifies the frequency of output clock output
OC6. The frequencies of the T0 APLL and T4 APLL are configured in the
Digital1 and Digital2 frequencies are configured in the
set by the O6F[2:0] bits, see
AOF6=0: (standard decodes)
AOF6=1: (alternate decodes)
Confidential. Document Issued Under Non-Disclosure Agreement. Confidential. Document Issued Under Non-Disclosure Agreement.
0000 = Output disabled (i.e. low)
0001 = 2 kHz
0010 = 8 kHz
0011 = T0 APLL frequency divided by 2
0100 = Digital1 (see
0101 = T0 APLL frequency
0110 = T0 APLL frequency divided by 16
0111 = T0 APLL frequency divided by 12
1000 = T0 APLL frequency divided by 8
1001 = T0 APLL frequency divided by 6
1010 = T0 APLL frequency divided by 4
1011 = T4 APLL frequency divided by 64
1100 = T4 APLL frequency divided by 48
1101 = T4 APLL frequency divided by 16
1110 = T4 APLL frequency divided by 8
1111 = T4 APLL frequency divided by 4
0000 = Output disabled (i.e. low)
0001 = T4 APLL frequency divided by 5
0010 = T4 APLL frequency divided by 2
0011 = T4 APLL frequency
0100 = T0 APLL2 frequency divided by 5
0101 = T0 APLL2 frequency divided by 2
0110 = T0 APLL2 frequency
0111 = T4 selected reference (after dividing)
1000 to 1111 = undefined
Bit 7
Table
Table
Bit 6
OFREQ6[3:0]
OCR3
Output Configuration Register 3
62h
see below
7-17. The decode of this field is controlled by the value of the OCR5.AOF6 bit.
7-7)
Preliminary. Subject to Change Without Notice.
Bit 5
76 of 110
MCR7
Bit 4
register. See section 7.8.2.3. The default frequency is
Bit 3
0
0
T0CR1
Bit 2
0
0
and
T4CR1
Bit 1
0
0
registers. The
Bit 0
DS3105
0
0