DS3105 Maxim Integrated Products, DS3105 Datasheet - Page 79

• Manufacturer Part Number: DS3105
• Description: Line Card Timing IC
• Manufacturer: Maxim Integrated Products

Register Name:
Register Description:
Register Address:
Name
Default
Bits 2 to 0: T4 DPLL Bandwidth (T4BW[2:0]). See section 7.7.3.
Register Name:
Register Description:
Register Address:
Name
Default
Bit 4: Reserved Bit 1 (RSV1). This bit is reserved for future use, it can be written to and read back.
Bit 3: Reserved Bit 2 (RSV2). This bit is reserved for future use, it can be written to and read back.
Bits 2 to 0: T0 DPLL Locked Bandwidth (T0LBW[2:0]). This field configures the bandwidth of the T0 DPLL when
locked to an input clock. When AUTOBW=0 in the
and for locked operation. When AUTOBW=1,
used for locked operation. See section 7.7.3.
Confidential. Document Issued Under Non-Disclosure Agreement. Confidential. Document Issued Under Non-Disclosure Agreement.
000 = 18 Hz
001 = 35 Hz
010 = 70 Hz
011 = {unused value, undefined}
111 = 18 Hz
000 = 35 Hz (default)
001 = 70 Hz
010 = {unused value, undefined}
011 = 18 Hz
100 = 120 Hz
101 = 250 Hz
110 = 400 Hz
Bit 7
Bit 7
0
0
0
0
Bit 6
Bit 6
0
0
0
0
T4BW
T4 Bandwidth Register
66h
T0LBW
T0 DPLL Locked Bandwidth Register
67h
Preliminary. Subject to Change Without Notice.
Bit 5
Bit 5
0
0
0
0
T0ABW
MCR9
79 of 110
RSV1
Bit 4
Bit 4
bandwidth is used for acquisition while T0LBW bandwidth is
0
0
0
register, the T0LBW bandwidth is used for acquisition
RSV2
Bit 3
Bit 3
0
0
0
Bit 2
Bit 2
0
0
0
T0LBW[2:0]
Bit 1
Bit 1
0
0
T4BW[1:0]
Bit 0
Bit 0
DS3105
0
0