DS3105 Maxim Integrated Products, DS3105 Datasheet - Page 62

• Manufacturer Part Number: DS3105
• Description: Line Card Timing IC
• Manufacturer: Maxim Integrated Products

Register Name:
Register Description:
Register Address:
Name
Default
Bit 7: Auto External Frame Sync Enable (AEFSEN). This bit has two modes depending on the SOURCE field of
FSCR3. See section 7.9.
SOURCE != 11XX:
SOURCE = 11XX:
Bit 6: Phase Lock Alarm Timeout (LKATO). This bit controls how phase alarms on input clocks can be
terminated. Phase alarms are indicated by the LOCK bits in
Bit 5: Local Oscillator Edge (XOEDGE). This bit specifies the significant clock edge of the local oscillator clock
signal on the REFCLK input pin. The faster edge should be selected for best jitter performance. See section 7.3.
Bit 4: Free-Run Holdover (FRUNHO). When this bit is set to 1 the T0 DPLL holdover frequency is set to 0 ppm so
the output frequency accuracy is set by the external oscillator accuracy. This effects both mini-holdover and the
holdover state.
Bit 3: External Frame Sync Enable (EFSEN). When this bit is set to 1 the T0 DPLL looks for a frame sync pulse
on the SYNCn pin(s). When FSCR3.SOURCE=11XX the function of this bit can be modified according to the
setting of the AEFSEN bit. See the AEFSEN bit description above for more information. See section 7.9.
Bit 2: SONET or SDH Frequencies (SONSDH). This bit specifies the clock rate for input clocks with FREQ=0001
in the
section 7.4.2.
Bit 0: Revertive Mode (REVERT). This bit configures the T0 DPLL for revertive or non-revertive operation. (The
T4 DPLL is always revertive). In revertive mode, if an input clock with a higher priority than the selected reference
becomes valid, the higher-priority reference immediately becomes the selected reference. In non-revertive mode
the higher-priority reference does not immediately become the selected reference but does become the highest-
priority reference in the priority table (REF1 field in the
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ICR
0 = EFSEN bit (bit 3 below) enables and disables the external frame sync on the SYNCn pin
1 = The external frame sync is enabled when EFSEN=1 and the T0 DPLL is locked to the input clock
0 = External frame sync enabled according to EFSEN bit.
1 = When the selected reference changes the EFSEN bit clears and the external frame sync is disabled.
0 = Phase alarms on input clocks can only be cancelled by software.
1 = Phase alarms are automatically cancelled after a time-out period of 128 seconds.
0 = Rising edge
1 = Falling edge
0 = Digital holdover
1 = Free-Run holdover, 0 ppm
0 = Disable external frame sync; ignore SYNCn pin(s)
1 = Enable external frame sync on SYNCn pin(s)
0 = 2048 kHz
1 = 1544 kHz.
registers (20h to 28h). During reset the default value of this bit is latched from the SONSDH pin. See
specified in the SOURCE field of FSCR3.
(EFSEN bit must be set to enable it again.)
AEFSEN
Bit 7
1
LKATO
Bit 6
1
MCR3
Master Configuration Register 3
34h
Preliminary. Subject to Change Without Notice.
XOEDGE
Bit 5
0
FRUNHO
62 of 110
Bit 4
PTAB1
0
ISR
register). See section 7.6.2.
registers.
EFSEN
Bit 3
1
see below
SONSDH
Bit 2
Bit 1
--
1
REVERT
Bit 0
DS3105
0