DS3105 Maxim Integrated Products, DS3105 Datasheet - Page 32

• Manufacturer Part Number: DS3105
• Description: Line Card Timing IC
• Manufacturer: Maxim Integrated Products

The DIG1 DFS can generate an NxDS1 or NxE1 signal with about 1 ns pk-pk jitter. The DIG2 DFS can generate an
NxDS1, NxE1, 6.312 MHz, 10 MHz or Nx19.44 MHz clock with approximately 1 ns pk-pk jitter. The frequency of the
DIG1 clock is configured by the DIG1SS bit in
clock is configured by the DIG2AF and DIG2SS bits in
can be independently configured for any of the frequencies shown in
The APLL DFS blocks and their associated output APLLs and output dividers can generate many different
frequencies. The APLL DFS blocks are always connected to the T0 DPLL. The T0 APLL frequencies that can be
generated are listed in
that can be generated are listed in
circuits are listed in
7.8.2.3
The following is a step-by-step procedure for configuring the frequencies of output clocks OC3 and OC6:
Table 7-14
the T4 APLL to obtain each frequency.
Table 7-7. Digital1 Frequencies
Confidential. Document Issued Under Non-Disclosure Agreement. Confidential. Document Issued Under Non-Disclosure Agreement.
DIG1F[1:0]
Setting in
MCR7
1. Use
2. Determine from
3. Configure the T0FREQ field in register T0CR1 as shown in Table 7-10 for the T0 APLL
Using
00
01
10
11
00
01
10
11
OC3 and OC6 Configuration
lists all possible frequencies for the output clocks and specifies how to configure the T0 APLL and/or
only generate one set of output frequencies. (In SONET/SDH equipment the T0 APLL is
typically configured for a frequency of 311.04 MHz in order to get Nx19.44 MHz output clocks
for use on line cards.)
chosen in step 2.
frequency determined in step 3. Configure fields T4CR1:T4FREQ, T0CR1:T4APT0 and
T0CR1:T0FT4 as shown in Table 7-12 for the T4 APLL frequency determined in step 3.
OFREQn fields of registers
Table 7-9
Table 7-9
Table
Table
Setting in
DIG1SS
and
MCR6
7-9.
to select a set of output frequencies for each APLL, T0 and T4. Each APLL can
0
0
0
0
1
1
1
1
Table 7-9
Table
7-10. The T0 APLL2 frequency is always 312.500 MHz. The T4 APLL frequencies
7-13, configure the frequencies of output clocks OC3 and OC6 in the
Preliminary. Subject to Change Without Notice.
Table
Table 7-14
the T0 and T4 APLL frequencies required for the frequency sets
OCR2
Frequency, MHz
7-12. The output frequencies that can be generated from the APLL
MCR6
and
16.384
12.352
2.048
4.096
8.192
1.544
3.088
6.176
also indicates the expected jitter amplitude for each frequency.
OCR4
32 of 110
and the DIG1F[1:0] field in MCR7. The frequency of the DIG2
MCR6
and the AOFn bits in the
Jitter, pk-pk nsec,
and the DIG2F[1:0] field in MCR7. DIG1 and DIG2
< 1
< 1
< 1
< 1
< 1
< 1
< 1
< 1
typical
Table 7-7
and
OCR5
Table
7-8, respectively.
register.
DS3105