DS3105 Maxim Integrated Products, DS3105 Datasheet - Page 67

• Manufacturer Part Number: DS3105
• Description: Line Card Timing IC
• Manufacturer: Maxim Integrated Products

Register Name:
Register Description:
Register Address:
Name
Default
The MCLK1 and MCLK2 registers must be read consecutively and written consecutively. See section 8.3.
Bits 7 to 0: Master Clock Frequency Adjustment (MCLKFREQ[7:0]). The full 16-bit MCLKFREQ[15:0] field
spans this register and
204.8MHz master clock with respect to the frequency of the local oscillator clock on the REFCLK pin by up to
+514ppm and –771 ppm. The master clock adjustment has the effect of speeding up the master clock with a
positive adjustment and slowing it down with a negative adjustment. For example, if the oscillator connected to
REFCLK has an offset of +1 ppm then the adjustment should be -1 ppm to correct the offset.
The formulas below translate adjustments to register values and vice versa. The default register value of 39,321
corresponds to 0 ppm. See section 7.3.
Register Name:
Register Description:
Register Address:
Name
Default
Bits 7 to 0: Master Clock Frequency Adjustment (MCLKFREQ[15:8]). See the
Register Name:
Register Description:
Register Address:
Name
Default
See section
Bit 7: Averaging (AVG). When this bit is set to 1 the T0 DPLL uses the averaged frequency value during holdover
mode. When FRUNHO=1 in the
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MCLKFREQ[15:0] = adjustment_in_ppm / 0.0196229 + 39,321
adjustment_in_ppm = ( MCLKFREQ[15:0] – 39,321 ) * 0.0196229
0 = Not averaged frequency; holdover frequency is either freerun (FRUNHO=1) or instantaneously frozen
1 = Averaged frequency over the last 1 second while locked to the input
8.3
Bit 7
Bit 7
for important information about writing and reading this register.
Bit 7
AVG
1
1
1
MCLK2.
Bit 6
Bit 6
Bit 6
--
0
0
0
MCR3
MCLK1
Master Clock Frequency Adjustment Register 1
3Ch
MCLK2
Master Clock Frequency Adjustment Register 2
3Dh
HOCR3
Holdover Configuration Register 3
40h
MCLKFREQ is an unsigned integer that adjusts the frequency of the internal
Preliminary. Subject to Change Without Notice.
register, this bit is ignored. See section 7.7.1.6.
Bit 5
Bit 5
Bit 5
--
0
0
0
67 of 110
MLCKFREQ[15:8]
Bit 4
Bit 4
Bit 4
MCLKFREQ[7:0]
1
1
0
--
Bit 3
Bit 3
Bit 3
1
1
1
Bit 2
Bit 2
Bit 2
0
0
0
MCLK1
register description.
Bit 1
Bit 1
Bit 1
--
0
0
0
Bit 0
Bit 0
Bit 0
DS3105
1
1
0