DS3105 Maxim Integrated Products, DS3105 Datasheet - Page 15

• Manufacturer Part Number: DS3105
• Description: Line Card Timing IC
• Manufacturer: Maxim Integrated Products

7 FUNCTIONAL DESCRIPTION
7.1 Overview
The DS3105 has five input clocks and two output clocks. There are two separate DPLLs in the device: the high-
performance T0 DPLL and the simpler T4 DPLL. The T0 DPLL can generate output clocks, the T4 DPLL can be
used to monitor inputs for frequency and phase. See
Three of the input clock pins are single-ended and can accept clock signals from 2 kHz to 125 MHz. The other two
are differential inputs that can accept clock signals up to 156.25 MHz. The differential inputs can be configured to
accept differential LVDS or LVPECL signals or single-ended CMOS/TTL signals.
Each input clock can be monitored continually for activity, and each can be marked unavailable or given a priority
number. Separate input priority numbers are maintained for the T0 DPLL and the T4 DPLL. Except in special
modes, the highest priority valid input is automatically selected as the reference for the T0 DPLL. SRFAIL is set or
cleared based on activity and/or frequency of the selected input.
Both the T0 DPLL and the T4 DPLL can directly lock to many common telecom and datacom frequencies,
including, but not limited to 8 kHz, DS1, E1, 10 MHz, 19.44 MHz, and 38.88 MHz as well as Ethernet frequencies
including 25 MHz, 62.5 MHz, 125 MHz and 156.25 MHz. The DPLLs can also lock to multiples of the standard
direct-lock frequencies including 8 kHz.
The T0 DPLL is the high-performance path with all the features needed for synchronizing a line card to dual
redundant system timing cards. The T4 DPLL can be used to monitor input clock signals but it can not drive any
output clocks. The T4 APLL is always connected to the T0 DPLL to provide low-jitter output frequencies from the
T0 DPLL. There is also a dedicated low-jitter APLL output that operates at 312.5 MHz for 10G Ethernet
applications.
Using the optional PLL bypass, the T4 selected reference, after any frequency division, can be directly output on
either of the OC3 or OC6 output clock pins.
Both DPLLs have these features:
The T0 DPLL has these additional features not available in the T4 DPLL:
The T4 DPLL has these additional features not available in the T0 DPLL:
Typically the internal state machine controls the T0 DPLL, but manual control by system software is also available.
The T4 DPLL has a simpler state machine that software can not directly control. In either DPLL, however, software
can override the DPLL logic using manual reference selection.
The outputs of the T0 DPLL can be connected to seven output DFS engines. See
DFS engines are associated with high-speed APLLs that multiply the DPLL clock rate and filter DPLL output jitter.
Confidential. Document Issued Under Non-Disclosure Agreement. Confidential. Document Issued Under Non-Disclosure Agreement.
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Automatic reference selection based on input activity and priority
Manual reference selection/forcing
Adjustable PLL characteristics, including bandwidth, pull-in range, and damping factor
Ability to lock to several common telecom and ethernet frequencies plus multiples of any standard
direct lock frequency.
Six bandwidth selections from 18 Hz to 400 Hz
A full state machine for automatic transitions among free-run, locked, and holdover states
Optional manual reference switching mode
Non-revertive reference switching mode
Phase build-out for reference switching (“hitless”)
Output vs. input phase offset control
Noise rejection circuitry for low-frequency references
Output phase alignment to input frame sync signal
Instant digital one-second averaging and free-run holdover modes
Frequency conversion between input and output using digital frequency synthesis
Optional mode to measure the phase difference between two input clocks
Preliminary. Subject to Change Without Notice.
Figure
15 of 110
3-1.
Figure
7-1. Three of these output
DS3105