DS3105 Maxim Integrated Products, DS3105 Datasheet - Page 85

• Manufacturer Part Number: DS3105
• Description: Line Card Timing IC
• Manufacturer: Maxim Integrated Products

Register Name:
Register Description:
Register Address:
Name
Default
Bit 3: GPIO4 State (GPIO4). This bit indicates the current state of the GPIO4 pin.
Bit 2: GPIO3 State (GPIO3). This bit indicates the current state of the GPIO3 pin.
Bit 2: GPIO2 State (GPIO2). This bit indicates the current state of the GPIO2 pin.
Bit 1: GPIO1 State (GPIO1). This bit indicates the current state of the GPIO1 pin.
Register Name:
Register Description:
Register Address:
Name
Default
The OFFSET1 and OFFSET2 registers must be read consecutively and written consecutively. See section 8.3.
Bits 7 to 0: Phase Offset (OFFSET[7:0]). The full 16-bit OFFSET[15:0] field spans this register and the
register. OFFSET is a 2’s-complement signed integer that specifies the desired phase offset between the output
clocks and the selected input reference. The phase offset in picoseconds is equal to OFFSET[15:0] *
actual_internal_clock_period / 2
offset equation simplifies to OFFSET[15:0] * 6.279 ps. If, however, the DPLL is locked to a reference whose
frequency is +1 ppm from ideal, for example, then the actual internal clock period is 1 ppm shorter and the phase
offset is 1 ppm smaller. When the OFFSET field is written, the phase of the output clocks is automatically ramped
to the new offset value to avoid loss of synchronization. To adjust the phase offset without changing the phase of
the output clocks, use the recalibration process enabled by FSCR3:RECAL. The OFFSET field is ignored when
phase build-out is enabled (PBOEN=1 in the
Register Name:
Register Description:
Register Address:
Name
Default
Bits 7 to 0: Phase Offset (OFFSET[15:8]). See the
Confidential. Document Issued Under Non-Disclosure Agreement. Confidential. Document Issued Under Non-Disclosure Agreement.
0 = low
1 = high
0 = low
1 = high
0 = low
1 = high
0 = low
1 = high
Bit 7
Bit 7
Bit 7
--
0
0
0
Bit 6
Bit 6
Bit 6
--
0
0
0
11
GPSR
GPIO Status Register
6Fh
OFFSET1
Phase Offset Register 1
70h
OFFSET2
Phase Offset Register 2
71h
. If the internal clock is at its nominal frequency of 77.76 MHz then the phase
Preliminary. Subject to Change Without Notice.
Bit 5
Bit 5
Bit 5
--
0
0
0
MCR10
OFFSET1
85 of 110
register) and when the DPLL is not locked. See section 7.7.8.
Bit 4
Bit 4
Bit 4
OFFSET[15:8]
--
0
0
0
OFFSET[7:0]
register description.
GPIO4
Bit 3
Bit 3
Bit 3
0
0
0
GPIO3
Bit 2
Bit 2
Bit 2
1
0
0
GPIO2
Bit 1
Bit 1
Bit 1
0
0
0
OFFSET2
GPIO1
Bit 0
Bit 0
Bit 0
DS3105
0
0
0