DS3105 Maxim Integrated Products, DS3105 Datasheet - Page 22

• Manufacturer Part Number: DS3105
• Description: Line Card Timing IC
• Manufacturer: Maxim Integrated Products

7.7 DPLL Architecture and Configuration
Both the T0 DPLL and T4 DPLL are digital PLLs. The T0 DPLL has separate analog PLLs (APLLs) as output
stages as well as some outputs that are not cleaned up by an APLL. This architecture combines the benefits of
both PLL types. See
Figure 7-1. DPLL Block Diagram
Digital PLLs have two key benefits: (1) stable, repeatable performance that is insensitive to process variations,
temperature and voltage, and (2) flexible behavior that is easily programmed via configuration registers. DPLLs use
digital frequency synthesis (DFS) to generate various clocks. In DFS a high-speed master clock (204.8 MHz) is
multiplied up from the 12.800 MHz local oscillator clock applied to the REFCLK pin. This master clock is then
digitally divided down to the desired output frequency. The DFS output clock has jitter of about 1 nsec pk-pk.
The analog PLLs filter the jitter from the DPLLs, reducing the 1 ns pk-pk jitter to less than 0.5 ns pk-pk and 60 ps
RMS, typical, measured broadband (10 Hz to 1 GHz).
T0 selected
T4 selected
reference
reference
Confidential. Document Issued Under Non-Disclosure Agreement. Confidential. Document Issued Under Non-Disclosure Agreement.
SYNC2K
Frequency
Locking
Loop Filter
Loop Filter
PFD and
PFD and
Frequency
Locking
SYNC2K
T0CR1:T4MT0
T4
T0
Figure
T4 DPLL
T0 DPLL
0
1
7-1.
ICRn:FREQ[3:0]
Feedback
ICRn:FREQ[3:0]
Feedback
Foward
Foward
DFS
DFS
T0
T0
DFS
DFS
T4
T4
Preliminary. Subject to Change Without Notice.
OUTPUT DFS
22 of 110
T4CR1:T4FREQ[3:0]
T0CR1:T0FREQ[2:0]
T0CR1:T0FT4[2:0]
MCR6:DIG1F[1:0]
MCR6:DIG2F[1:0]
MCR6:DIG1SS
MCR6:DIG2SS
MCR6:DIG2AF
FSYNC
APLL2
DIG12
DIG12
APLL
APLL
2K8K
DFS
DFS
DFS
DFS
DFS
DFS
DFS
T4
T0
T0
2
FSCR2:INDEP
Output
Output
Output
PLL Bypass
APLL2
APLL
APLL
T4
T0
T0
2K8K
DIG1
DIG2
2
Dividers
Dividers
Dividers
Output
Output
Output
APLL
APLL
APLL
FSCR1:8KPOL, 2KPOL
FSCR1:8KINV, 2KINV
OCR4:FSEN, MFSEN
OCRm:OFREQn[3:0]
OCR5:AOFn
OC3, OC6
FSYNC,
MFSYNC
DS3105