DS3105 Maxim Integrated Products, DS3105 Datasheet - Page 24

• Manufacturer Part Number: DS3105
• Description: Line Card Timing IC
• Manufacturer: Maxim Integrated Products

Figure 7-2. T0 DPLL State Transition Diagram
• An input clock is valid when it has no activity alarm and no phase lock alarm (see the
• All input clocks are continuously monitored for activity.
• Only the selected reference is monitored for loss of lock.
• Phase lock is declared internally when the DPLL has maintained phase lock continuously for approximately 1 to 2 seconds.
• To simply the diagram, the phase-lock time-out period is always shown as 100s, which is the default value of the
• When selected reference is invalid and the DPLL is not in freerun or holdover, the DPLL is in a temporary holdover state.
7.7.1.3
The T0 DPLL state machine can reach the locked state from the pre-locked, pre-locked 2 or loss-of-lock states
when the DPLL has locked to the selected reference for at least two seconds (see section 7.7.6). In the locked
state the output clocks track the phase and frequency of the selected reference.
If the MCR1.LOCKPIN bit is set, the LOCK pin is driven high when the T0 DPLL is in the Locked state.
While in the locked state, if the selected reference is so impaired that an activity alarm is raised (corresponding
ACT bit set in the
and the state machine immediately transitions to either the pre-locked 2 state (if another valid input clock is
available) or, after being invalid for 2 seconds, to the holdover state (if no other input clock is valid).
If loss-of-lock (see section 7.7.6) is declared while in the locked state then the state machine transitions to the loss-
of-lock state.
Notes:
shorter time-out periods can be specified as needed by writing the appropriate value to the
Confidential. Document Issued Under Non-Disclosure Agreement. Confidential. Document Issued Under Non-Disclosure Agreement.
(revertive mode AND valid higher-priority input)]
(revertive mode AND valid higher-priority input)]
Locked State
AND valid input clock available
[selected reference invalid OR
wait for <=100s
AND valid input clock available
[selected reference invalid OR
Pre-locked 2
(revertive mode AND valid higher-priority input)]
out of lock >100s OR
(101)
ISR
register), then the selected reference is invalidated (ICn bit goes low in
(revertive mode AND valid higher-priority input)
AND valid input clock available
[selected reference invalid OR
phase-locked
to selected
reference > 2s
[selected reference invalid OR
OR out of lock >100s] AND
valid input clock available
out of lock >100s OR
(selected reference invalid > 2s
AND no valid input clock
OR out of lock >100s)
Preliminary. Subject to Change Without Notice.
Reset
on selected reference
phase-lock regained
within 100s
(selected reference invalid > 2s
no valid input clock available
OR out of lock >100s) AND
all input clocks evaluated
at least one input valid
24 of 110
wait for <=100s
wait for <=100s
Loss-of-Lock
Pre-locked
Free-Run
select ref
Locked
(001)
(110)
(100)
(111)
phase-locked to
selected reference > 2s
loss-of-lock on
selected reference
all input clocks evaluated
at least one input valid
(selected reference invalid > 2s
no valid input clock available
OR out of lock >100s) AND
VALSR
PHLKTO
registers and the
register.
selected reference invalid > 2s
no valid input clock available
ISR
AND
select ref
PHLKTO
Holdover
(010)
registers).
VALSR
register. Longer or
registers),
DS3105