DS3105 Maxim Integrated Products, DS3105 Datasheet - Page 13

• Manufacturer Part Number: DS3105
• Description: Line Card Timing IC
• Manufacturer: Maxim Integrated Products

Table 6-4. SPI Bus Mode Pin Descriptions
See section
Table 6-5. JTAG Interface Pin Descriptions
See section
Table 6-6. Power Supply Pin Descriptions
Pin Name
CS
SCLK
SDI
SDO
CPHA
Pin Name
JTRST
JTCLK
JTDI
JTDO
JTMS
Pin Name
VDD
VDDIO
VSS
AVDD_DL
AVSS_DL
VDD_OC6
VSS_OC6
AVDD_PLL1
AVSS_PLL1
AVDD_PLL2
AVSS_PLL2
AVDD_PLL3
AVSS_PLL3
AVDD_PLL4
AVSS_PLL4
Confidential. Document Issued Under Non-Disclosure Agreement. Confidential. Document Issued Under Non-Disclosure Agreement.
7.10
9
for functional description and section
(1)
(1)
(1)
for functional description and section
Type
Type
Type
I
I
I
O
I
O
PU
PU
PU
PU
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
I
I
I
I
3
(2)
(2)
(2)
Pin Description
Chip Select.
This pin must be asserted (low) to read or write internal registers.
Serial Clock.
SCLK is always driven by the SPI bus master.
Serial Data Input.
The SPI bus master transmits data to the device on this pin.
Serial Data Output.
The device transmits data to the SPI bus master on this pin.
Clock Phase
See
0 = data is latched on the leading edge of the SCLK pulse
1 = data is latched on the trailing edge of the SCLK pulse
Pin Description
JTAG Test Reset (active low).
Asynchronously resets the test access port (TAP) controller. If not used, JTRST can be held low
or high.
JTAG Clock,
Shifts data into JTDI on the rising edge and out of JTDO on the falling edge. If not used, JTCLK
can be held low or high.
JTAG Test Data Input.
Test instructions and data are clocked in on this pin on the rising edge of JTCLK. If not used,
JTDI can be held low or high.
JTAG Test Data Output.
Test instructions and data are clocked out on this pin on the falling edge of JTCLK. If not used,
leave floating.
JTAG Test Mode Select.
Sampled on the rising edge of JTCLK and is used to place the port into the various defined
IEEE 1149.1 states. If not used connect to VDDIO or leave floating.
Pin Description
Core Power Supply. 1.8V ±10%.
I/O Power Supply. 3.3V ±5%.
Ground Reference .
Power Supply for OC6 Digital Logic. 1.8V ±10%.
Return for OC6 Digital Logic.
Power Supply for Differential Output OC6POS/NEG. 1.8V ±10%.
Return for LVDS Differential Output OC6POS/NEG.
Power Supply for Master Clock Generator APLL. 1.8V ±10%.
Return for Master Clock Generator APLL.
Power Supply for T0 APLL. 1.8V ±10%.
Return for T0 APLL.
Power Supply for T4 APLL. 1.8V ±10%.
Return for T4 APLL.
Power Supply for T0 APLL2. 1.8V ±10%.
Return for T0 APLL2.
Figure
Preliminary. Subject to Change Without Notice.
7-4.
10.5
10.4
for timing specifications.
for timing specifications.
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DS3105