DS3105 Maxim Integrated Products, DS3105 Datasheet - Page 16

• Manufacturer Part Number: DS3105
• Description: Line Card Timing IC
• Manufacturer: Maxim Integrated Products

Preliminary. Subject to Change Without Notice.
DS3105
The outputs of the APLLs are divided down to make a wide variety of possible frequencies available at the output
clock pins. The output frequencies from the T0 DPLL can be synchronized to an input 2, 4 or 8 kHz sync signal
(SYNC1, SYNC2 or SYNC3 input pins).
The OC3 and OC6 output clocks can be configured for a variety of different frequencies that are frequency and
phase locked to the T0 DPLL. The OC6 output is LVDS/LVPECL. The OC3 output is CMOS. Altogether more than
60 output frequencies are possible, ranging from 2 kHz to 312.5 MHz. The FSYNC output clock is always 8 kHz,
and the MFSYNC output clock is always 2 kHz.
7.2 Device Identification and Protection
The 16-bit read-only ID field in the
ID1
and
ID2
registers is set to 0C21h = 3105 decimal. The device revision can
be read from the
REV
register. Contact the factory to interpret this value and determine the latest revision. The
register set can be protected from inadvertent writes using the
PROT
register.
7.3 Local Oscillator and Master Clock Configuration
The T0 DPLL, the T4 DPLL and the output DFS engines operate from a 204.8 MHz master clock. The master
clock is synthesized from a 12.800 MHz clock originating from a local oscillator attached to the REFCLK pin. The
stability of the T0 DPLL in freerun or holdover is equivalent to the stability of the local oscillator. Selection of an
appropriate local oscillator is therefore of crucial importance if the telecom standards listed in
Table 1-1
are to be
met. Simple XOs can be used in less stringent cases, but TCXOs or even OCXOs may be required in the most
demanding applications. Careful evaluation of the local oscillator component is necessary to ensure proper
performance. Contact Dallas/Maxim at
[e-mail]
for recommended oscillators.
The stability of the local oscillator is very important, but its absolute frequency accuracy is less important because
the DPLLs can compensate for frequency inaccuracies when synthesizing the 204.8 MHz master clock from the
local oscillator clock. The MCLKFREQ field in registers
MCLK1
and
MCLK2
specifies the frequency adjustment to
be applied. The adjust can be from –771 ppm to +514 ppm in 0.0196229 ppm (i.e. ~0.02 ppm) steps.
7.4 Input Clock Configuration
The DS3105 has five input clocks, IC3 to IC6 and IC9.
Table 7-1
provides summary information about each clock,
including signal format and available frequencies. The device tolerates a wide range of duty cycles on input clocks,
out to a minimum high time or minimum low time of 3 ns or 30% of the clock period, whichever is smaller.
7.4.1 Signal Format Configuration
Inputs with CMOS/TTL signal format accept both TTL and 3.3V CMOS levels. One key configuration bit that affects
the available frequencies is the SONSDH bit in MCR3. When SONSDH=1 (SONET mode), the 1.544 MHz
frequency is available. When SONSDH=0 (SDH mode), the 2.048 MHz frequency is available. During reset the
default value of this bit is latched from the SONSDH pin.
Input clocks IC5 and IC6 can be configured to accept LVDS, LVPECL, or CMOS/TTL signals by using the proper
Figure 10-1
while the recommended
set of external components. The recommended LVDS termination is shown in
LVPECL termination is shown in
Figure
10-2. The electrical specifications for these inputs are listed in
Table
10-4.
To configure these differential inputs to accept single-ended CMOS/TTL signals, use a voltage divider to bias the
ICxNEG pin to approximately 1.4V and connect the single-ended signal to the ICxPOS pin. If a differential input is
not used it should be left floating (one input is internally pulled high and the other internally pulled low). (See also
MCR5:IC5SF and IC6SF.)
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