DS3105 Maxim Integrated Products, DS3105 Datasheet - Page 19

• Manufacturer Part Number: DS3105
• Description: Line Card Timing IC
• Manufacturer: Maxim Integrated Products

Preliminary. Subject to Change Without Notice.
DS3105
7.5.3 Selected Reference Activity Monitoring
The input clock that each DPLL is currently locked to is called the selected reference. The quality of a DPLL’s
selected reference is exceedingly important, since missing cycles and other anomalies on the selected reference
can cause unwanted jitter, wander or frequency offset on the output clocks. When anomalies occur on the selected
reference they must be detected as soon as possible to give the DPLL opportunity to temporarily disconnect from
the reference until the reference is available again. By design, the regular input clock activity monitor (section 7.5.2)
is too slow to be suitable for monitoring the selected reference. Instead, each DPLL has its own fast activity monitor
that detects that the frequency is within range (approximately 10,000 ppm) and detects inactivity within
approximately two missing reference clock cycles (approximately four missing cycles for 156.25 MHz, 155.52 MHz,
125 MHz, 62.5 MHz, 25 MHz and 10 MHz references).
When the T0 DPLL detects a no-activity event, it immediately enters mini-holdover mode to isolate itself from the
selected reference and sets the SRFAIL latched status bit in MSR2. The setting of the SRFAIL bit can cause an
interrupt request if the corresponding enable bit is set in IER2. If MCR10:SRFPIN=1, the SRFAIL output pin follows
the state of the SRFAIL status bit. Optionally, a no-activity event can also cause an ultra-fast reference switch (see
section 7.6.4). When PHLIM1:NALOL=0 (default), the T0 DPLL does not declare loss-of-lock during no-activity
events. If the selected reference becomes available again before any alarms are declared by the activity monitor,
then the T0 DPLL continues to track the selected reference using nearest-edge locking (±180°) to avoid cycle slips.
When NALOL=1, the T0 DPLL declares loss-of-lock during no-activity events. This causes the T0 DPLL state
machine to transition to the loss-of-lock state, which sets the MSR2:STATE bit and causes an interrupt request if
enabled. If the selected reference becomes available again before any alarms are declared by the activity monitor,
then the T0 DPLL tracks the selected reference using phase/frequency locking (±360°) until phase lock is
reestablished.
When the T4 DPLL detects a no-activity event, its behavior is similar to the T0 DPLL with respect to the
PHLIM1:NALOL control bit. Unlike the T0 DPLL, however, the T4 DPLL does not set the SRFAIL status bit. If
NALOL=1, the T4 DPLL clears the OPSTATE:T4LOCK status bit, which sets MSR3:T4LOCK and causes an
interrupt request if enabled.
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