pic32mx320f064h Microchip Technology Inc., pic32mx320f064h Datasheet - Page 104

• Manufacturer Part Number: pic32mx320f064h
• Description: 64/100-pin General Purpose, 32-bit Flash Microcontrollers
• Manufacturer: Microchip Technology Inc.

PIC32MX FAMILY
5.11
The DMA device has the ability to generate interrupts
reflecting the events that occurr during the channel’s
data transfer. The different kinds of DMA interrupt flags
are:
• CHERIF (DCHxINT<0>): Channel Error
• CHTAIF (DCHxINT<1>): Channel Abort interrupts,
• CHBCIF (DCHxINT<3>): Channel Block complete
• CHCCIF (DCHxINT<2>): Channel Cell complete
• CHSDIF (DCHxINT<7>): Channel Source pointer
• CHSHIF (DCHxINT<6>): Channel Source pointer
• CHDDIF (DCHxINT<5>): Channel Destination
• CHDHIF (DCHxINT<4>): Channel Destination
DS61143A-page 102
interrupts, enabled using CHERIE
(DCHxINT<16>).
enabled using CHTAIE (DCHxINT<17>).
interrupts, enabled using CHBCIE
(DCHxINT<19>).
interrupts, enabled using CHCCIE
(DCHxINT<18>).
reached the end of the source, enabled by
CHSDIE (DCHxINT<23>).
reached midpoint of the source, enabled by
CHSHIE (DCHxINT<22>).
Pointer reached the end of the destination,
enabled by CHDDIE (DCHxINT<21>)
Pointer reached midpoint of the destination,
enabled by CHDHIE (DCHxINT<20>).
DMA Interrupts
Advance Information
All the interrupts belonging to a DMA channel map to
the corresponding channel interrupt vector.
The corresponding interrupt flags are:
• DMA0IF (IFS1<16>)
• DMA1IF (IFS1<17>)
• DMA2IF (IFS1<18>)
• DMA3IF (IFS1<19>)
A DMA channel is enabled as a source of interrupts via
the respective DMA interrupt enable bits:
• DMA0IE (IEC1<16>)
• DMA1IE (IEC1<17>)
• DMA2IE (IEC1<18>)
• DMA3IE (IEC1<19>)
The interrupt priority level bits and interrupt subpriority
level bits must be also be configured:
• DMA0IP<2:0> (IPC9<4:2>), DMA0IS<1:0>
• DMA1IP<2:0> (IPC9<12:10>), DMA1IS<1:0>
• DMA2IP<2:0> (IPC9<20:18>), DMA2IS<1:0>
• DMA3IP<2:0> (IPC9<28:26>), DMA3IS<1:0>
In addition to enabling the DMA interrupts, Interrupt
Service Routines (ISRs) are required for each different
interrupt vector used.
Example 5-8.
All these interrupt flags must be cleared in software.
(IPC9<1:0>).
(IPC9<9:8>).
(IPC9<17:16>).
(IPC9<25:24>).
Note:
It is the user’s responsibility to clear the
corresponding interrupt flag bit before
returning from an ISR.
© 2007 Microchip Technology Inc.
See Example 5-7 and