pic32mx320f064h Microchip Technology Inc., pic32mx320f064h Datasheet - Page 194

• Manufacturer Part Number: pic32mx320f064h
• Description: 64/100-pin General Purpose, 32-bit Flash Microcontrollers
• Manufacturer: Microchip Technology Inc.

PIC32MX FAMILY
9.3
On any form of Reset, the interrupt controller initializes
to
(INTCON<12>) bit is ‘0’, the interrupt controller oper-
ates in Single Vector mode. In this mode, the CPU
always vectors to the same address.
EXAMPLE 9-1:
DS61143A-page 192
Note:
/*
*/
Single
Set the CP0 registers for multi-vector interrupt
Place EBASE at 0xBD000000
This code example uses MPLAB C32 intrinsic functions to access CP0 registers.
Check your compiler documentation to find equivalent functions or use inline assembly
unsigned int temp;
asm(“di”);
temp = _CP0_GET_STATUS();
temp |= 0x00400000;
_CP0_SET_STATUS(temp);
_CP0_SET_EBASE(0xBD000000);
_CP0_SET_INTCTL(0x00000020);
temp = _CP0_GET_CAUSE();
temp |= 0x00800000;
_CP0_SET_CAUSE(temp);
temp = _CP0_GET_STATUS();
temp &= 0xFFBFFFFD;
_CP0_SET_STATUS(temp);
INTCONCLR = 0x1000;
asm(“ei”);
Single Vector Mode
Users familiar with MIPS32 Architecture
must note that the M4K core in PIC32MX
Family is still operating in External Inter-
rupt Controller (EIC) mode. The PIC32MX
Family achieves Single Vector mode by
forcing all IRQs to use a vector number of
0x00. Because the M4K core in PIC32MX
Family always operates in EIC mode, the
single vector behavior through “Interrupt
Compatibility
MIPS32
recommended.
Vector
SINGLE VECTOR MODE INITIALIZATION
mode.
Architecture,
Mode,”
When
as
defined
the
is
Advance Information
MVEC
// Disable all interrupts
// Get Status
// Set BEV bit
// Update Status
// Set an EBase value of 0xBD000000
// Set the Vector Spacing to non-zero value
// Get Cause
// Set IV
// Update Cause
// Get Status
// Clear BEV and EXL
// Update Status
// Clear MVEC bit
// Enable all interrupts
not
by
To configure the CPU in Single Vector mode, the follow-
ing CPU registers (IntCtl, Cause, and Status) and
INTCON register must be configured as follows:
• EBase ≠ 00000
• VS (IntCtl<9:5>) ≠ 00000
• IV (Cause<23>) = 1
• EXL (Status<1>) = 0
• BEV (Status<22>) = 0
• MVEC (INTCON<12>) = 0
• IE (Status<0>) = 1
© 2007 Microchip Technology Inc.