pic32mx320f064h Microchip Technology Inc., pic32mx320f064h Datasheet - Page 389

• Manufacturer Part Number: pic32mx320f064h
• Description: 64/100-pin General Purpose, 32-bit Flash Microcontrollers
• Manufacturer: Microchip Technology Inc.

20.3
The PMP Master mode timing for control, address and
data signals is dependent on the PBCLK peripheral bus
clock speed, address/data multiplexing and number of
Wait states, if any. Table 20-7 provides a summary of
PMP read and write maximum sustainable speeds for
each of its Address Multiplex modes.
TABLE 20-7:
20.3.1
The Master mode configuration is determined primarily
by the interface requirements to the external device.
Address multiplexing, control signal polarity, data width
and Wait states typically dictate the specific configura-
tion of the PMP master port.
The following illustrates example settings for Master
Mode 2 operation:
• Select Master Mode 2 -
• Select 16-Bit Data mode -
• Select partial multiplexed addressing -
• Select auto-address increment -
• Enable Interrupt Request mode -
• Enable PMRD strobe -
• Enable PMWR strobe -
• Enable PMCS2 and PMCS1 chip selects -
• Select PMRD “active-low” pin polarity -
• Select PMWR “active-low” pin polarity -
• Select PMCS2, PMCS1 “active-low” pin polarity -
© 2007 Microchip Technology Inc.
Note 1:
MODE16 (PMMODE<10>) = 1.
ADRMUX<1:0> (PMCON<12:11>) = 01.
INCM<1:0> (PMMODE<12:11>) = 01.
IRQM<1:0> (PMMODE<14:13>) = 01.
Note:
MODE<1:0> (PMMODE<9:8>) = 10.
PTRDEN (PMCON<8>) = 1.
PTWREN (PMCON<9>) = 1.
CSF (PMCON<7:6>) = 10.
RDSP (PMCON<0>) = 0.
WRSP (PMCON<1>) = 0.
Full Multiplexed (16-bit data)
Full Multiplexed (8-bit data)
Multiplex Configuration
Master Mode Timing
Partial Multiplex
Address/Data
Demultiplexed
During any Master mode read or write
operation, the busy flag will always de-
assert 1 peripheral bus clock cycle
(T
including Wait states.
MASTER PORT CONFIGURATION
Peripheral bus clock operating at 1:1 with SYSCLK (72MHz)
PBCLK )
READ/WRITE SPEEDS, NO WAIT STATES
, before the end of the operation,
ADRMUX
Advance Information
00
01
10
11
Read
2
5
8
5
(PBCLK cycles)
PMP Operation
• Select 1 wait cycle for data setup -
• Select 2 wait cycles to extend PMRD/PMWR -
• Select 1 wait cycle for data hold -
• Enable upper 8 PMA<15:8> address pins -
(PMCON<3>) = 0.
WAITB<1:0>(PMMODE<7:6>) = 00.
WAITM<3:0>(PMMODE<5:2>) = 01.
WAITB<1:0>(PMMODE<1:0>) = 00.
PMAEN<15:8> = 1 (lower 8 can be used as
general purpose I/O).
CS2P (PMCON<4>) = 0 and CS1P
PIC32MX FAMILY
Write
3
6
9
6
Read
36.0
14.4
14.4
9.0
Speed
DS61143A-page 387
(1)
(MHz)
Write
24.0
12.0
12.0
8.0