pic32mx320f064h Microchip Technology Inc., pic32mx320f064h Datasheet - Page 386

• Manufacturer Part Number: pic32mx320f064h
• Description: 64/100-pin General Purpose, 32-bit Flash Microcontrollers
• Manufacturer: Microchip Technology Inc.

PIC32MX FAMILY
20.2.7
The PMP module supports two distinct read/write sig-
naling methods. In Master Mode 1, Read and Write
strobe are combined into a single control line, PMRD/
PMWR; a second control line, PMENB, determines
when a read or write action is to be taken.
In Master Mode 2, Read and Write strobes (PMRD and
PMWR) are supplied on separate pins.
To enable the PMRD/PMWR and PMWR/PMENB pins,
set PTRDEN bit (PMCON<8>) and
(PMCON<9>) = 1.
20.2.8
All control signals (PMRD, PMWR, PMALL, PMALH,
PMCS2 and PMCS1) can be individually configured for
either positive (active-high) or negative (active-low)
polarity. The polarity for each control line is controlled
by separate bits in the PMCON register.
TABLE 20-4:
Note that the polarity of control signals that share the
same output pin (for example, PMWR and PMENB) are
controlled by the same bit; the configuration depends
on which Master Port mode is being used.
20.2.9
While the module is operating in a Master mode, the
auto-address increment/decrement bits INCM<1:0>
(PMMODE<12:11>) control the behavior of the address
value that appears on the PMA<15:0> address pins.
The address can be made to automatically increment
or decrement after each read and write operation, once
each operation is completed, and the BUSY bit goes to
‘0’.
TABLE 20-5:
DS61143A -page 384
CONTROL
PMALL/H
INCM<1:0>
PMCS2
PMCS1
PMWR
PMRD
PIN
00
01
10
READ/WRITE CONTROL
CONTROL LINE POLARITY
AUTO-INCREMENT/DECREMENT
Control Bit
PMCON
WRSP
RDSP
CS2P
CS1P
ALP
MASTER MODE PIN
POLARITY
INCREMENT/DECREMENT
CONFIGURATION
ADDRESS AUTO-
No Increment, No Decrement
Decrement every R/W Cycle
Increment every R/W Cycle
Active-High
FUNCTION
Select
1
1
1
1
1
PTWREN bit
Active-Low
Advance Information
Select
0
0
0
0
0
If the Chip Select signals are disabled and configured
as address bits, the bits will participate in the increment
and decrement operations; otherwise, the PMCS2 and
PMCS1 bit values will be unaffected.
20.2.10
In Master modes, the user has control over the dura-
tion of the read, write, and address cycles by configur-
ing the module Wait states. Three portions of the
cycle, the beginning, middle, and end are configured
using the corresponding WAITB, WAITM, and WAITE
bits in the PMMODE register.
20.2.11
In either of the Master modes the address bus can be
multiplexed together with the data bus. There are three
Address Multiplexing modes available; Demultiplexed,
Partial Multiplexed and Full Multiplexed. The Address-
ing
ADRMUX<1:0> (PMCON<12:11).
For detailed examples illustrating address multiplexing
configurations, refer to the PMP chapter in the
“PIC32MX Family Reference Manual” (DS61132).
TABLE 20-6:
20.2.12
In Demultiplexed mode, address bits are presented on
pins PMA<15:0>.
PMCS2 is enabled and PMA14 is not available if
PMCS1 is enabled. Data bits are presented on pins
PMD<15:0> in 16-Bit Data mode; pins PMD<7:0> in 8-
Bit Data mode.
configuring bits ADRMUX<1:0> = 00.
ADRMUX<1:0>
Note:
Multiplex
00
01
10
11
WAIT STATES
ADDRESS MULTIPLEXING
DEMULTIPLEXED MODE
A design implementing partial or full mul-
tiplexed address and data bus allows the
unused PMA address pins to be used as
general purpose I/O pins.
depending on the Multiplexing mode, read
and write operations will be extended by
several peripheral bus clock cycles, T
CLK
.
mode
ADDRESS MULTIPLEX
CONFIGURATIONS
Demultiplexed mode is selected by
Note, PMA15 is not available if
© 2007 Microchip Technology Inc.
Partial (uses PMD<7:0>)
is
Full (uses PMD<15:0>)
Full (uses PMD<7:0>)
Multiplex Modes
configured
Demultiplexed
using
However,
PB-
bits