pic32mx320f064h Microchip Technology Inc., pic32mx320f064h Datasheet - Page 217

• Manufacturer Part Number: pic32mx320f064h
• Description: 64/100-pin General Purpose, 32-bit Flash Microcontrollers
• Manufacturer: Microchip Technology Inc.

10.2
The PIC32MX device has two internal clocks: CPU
clock and PB clock. They are derived from the currently
selected clock source. The clock source can be chosen
from the 4 available internal or external clock sources.
Some of these clock sources have Phase Locked
Loops (PLLs), programmable output dividers, or input
divider to scale the input frequency to suit the applica-
tion. The clock source can be changed on the fly by
software. The oscillator control register is locked by
hardware, it must be unlocked by a series of writes
before software can perform a clock switch.
There are two main clocks in the PIC32MX Family
device
• The System clock (SYSCLK) used by CPU and
• The Peripheral Bus Clock (PBCLK) used by most
The PIC32MX Family clocks are derived from one of
the following sources:
• Primary Oscillator (POSC) on the OSCI and
• Secondary Oscillator (SOSC) on the SOSCI and
• Internal Fast RC Oscillator (FRC)
• Internal Low-Power RC Oscillator (LPRC)
TABLE 10-2:
© 2007 Microchip Technology Inc.
Fast RC Oscillator with Postscaler (FRCDIV)
Fast RC Oscillator divided by 16 (FRCDIV16)
Low-Power RC Oscillator (LPRC)
Secondary (Timer1/RTCC) Oscillator (SOSC)
Primary Oscillator (HS) with PLL Module
(HSPLL)
Primary Oscillator (XT) with PLL Module
(XTPLL)
Primary Oscillator (EC) with PLL Module
(ECPLL)
Primary Oscillator (HS)
Primary Oscillator (XT)
Primary Oscillator (EC)
Fast RC Oscillator with PLL Module
(FRCPLL)
Fast RC Oscillator (FRC)
Note 1:
some peripherals
peripherals
OSCO pins
SOSCO pins
2:
3:
Operation: Clock Generation and
Clock Sources
OSCO pin function as PBCLK out or Digital I/O is determined by the OSCIOFNC Configuration bit. When
the pin is not required by the Oscillator mode it may be configured for one of these options.
Default Oscillator mode for an unprogrammed (erased) device.
When using the PLL modes the input divider must be chosen such that resulting frequency applied to the
PLL is in the range of 4 MHz to 5 MHz.
Oscillator Mode
CLOCK SELECTION CONFIGURATION BIT VALUES
Advance Information
Secondary
Oscillator
Source
Primary
Primary
Primary
Primary
Primary
Primary
Internal
Internal
Internal
Internal
Internal
Each of the clock sources has unique configurable
options, such as a PLL, input divider, and/or output
divider, that are detailed in their respective sections.
There are up to four internal clocks depending on the
specific device. The clocks are derived from the cur-
rently selected oscillator source.
10.2.1
The SYSCLK is the primary clock used by the CPU and
select peripherals such as DMA, Interrupt Controller,
and Prefetch Cache. The SYSCLK is derived from one
of the four clock sources: POSC, SOSC, FRC, and
LPRC. Some of the clock sources have specific clock
multipliers and/or divider options. No clock scaling is
applied other than the user specified values. The
SYSCLK source is selected by the device configuration
and can be changed by software during operation. The
ability to switch clock sources during operation allows
the application to reduce power consumption by reduc-
ing the clock speed. Refer to Table 10-2 for a list of
SYSCLK sources.
Note:
POSCMD<1:0>
PIC32MX FAMILY
Clock sources for peripherals that use
external clocks, such as the RTC and
Timer1, are covered in their respective
sections.
SYSTEM CLOCK (SYSCLK)
GENERATION
xx
xx
xx
xx
10
01
00
10
01
00
10
xx
FNOSC2:
FNOSC0
111
110
101
100
011
011
011
010
010
010
001
000
DS61143A-page 215
Notes
1, 2
1
1
1
3
3
3
1
1