pic32mx320f064h Microchip Technology Inc., pic32mx320f064h Datasheet - Page 207

• Manufacturer Part Number: pic32mx320f064h
• Description: 64/100-pin General Purpose, 32-bit Flash Microcontrollers
• Manufacturer: Microchip Technology Inc.

REGISTER 10-1:
© 2007 Microchip Technology Inc.
bit 20-19
bit 18-16
bit 15
bit 14-12
bit 11
bit 10-8
bit 7
bit 6
bit 5
bit 4
PBDIV<1:0>: Peripheral Bus Clock Divisor bits
11 = PBCLK is SYSCLK divided by 8
10 = PBCLK is SYSCLK divided by 4
01 = PBCLK is SYSCLK divided by 2
00 = PBCLK is SYSCLK divided by 1
Note: Initial value is loaded from DEVCFG1<13:12>.
PLLMULT<2:0>: PLL Multiplier bits
111 = Clock is multiplied by 24
110 = Clock is multiplied by 21
101 = Clock is multiplied by 20
100 = Clock is multiplied by 19
011 = Clock is multiplied by 18
010 = Clock is multiplied by 17
001 = Clock is multiplied by 16
000 = Clock is multiplied by 15
Note: On Reset these bits are set to the value of the FPLLMULT Configuration bits
Unimplemented: Read as ‘0’
COSC<2:0>: Current Oscillator Selection bits
111 = Fast Internal RC Oscillator divided by OSCCON.FRCDIV
110 = Fast Internal RC Oscillator divided by 16
101 = Low-Power Internal RC Oscillator (LPRC)
100 = Secondary Oscillator (SOSC)
011 = Primary Oscillator with PLL module (XTPLL, HSPLL or ECPLL)
010 = Primary Oscillator (XT, HS or EC)
001 = Fast RC Oscillator with PLL module via Postscaler (FRCPLL)
000 = Fast RC Oscillator (FRC)
Note: On Reset these bits are set to the value of the FNOSC Configuration bits (DEVCFG1<2:0>).
Unimplemented: Read as ‘0’
NOSC<2:0>: New Oscillator Selection bits
111 = Fast Internal RC Oscillator divided by OSCCON.FRCDIV
110 = Fast Internal RC Oscillator divided by 16
101 = Low-Power Internal RC Oscillator (LPRC)
100 = Secondary Oscillator (SOSC)
011 = Primary Oscillator with PLL module (XTPLL, HSPLL or ECPLL)
010 = Primary Oscillator (XT, HS or EC)
001 = Fast Internal RC Oscillator with PLL module via Postscaler (FRCPLL)
000 = Fast Internal RC Oscillator (FRC)
Note: On Reset these bits are set to the value of the FNOSC Configuration bits (DEVCFG1<2:0>).
CLKLOCK: Clock Selection Lock Enable bit
If FSCM is enabled (FCKSM1 =1):
1 = Clock and PLL selections are locked.
0 = Clock and PLL selections are not locked and may be modified
If FSCM is disabled (FCKSM1 =0):
Note: Clock and PLL selections are never locked and may be modified.
Reserved: Maintain as ‘0’
SLOCK: PLL Lock Status bit
1 = PLL module is in lock or PLL module start-up timer is satisfied
0 = PLL module is out of lock, PLL start-up timer is running or PLL is disabled
SLPEN: Sleep Mode Enable bit
1 = Device will enter Sleep mode when a WAIT instruction is executed
0 = Device will enter Idle mode when a WAIT instruction is executed
(DEVCFG2<6:4>).
OSCCON: OSCILLATOR CONTROL REGISTER
Advance Information
PIC32MX FAMILY
DS61143A-page 205