pic32mx320f064h Microchip Technology Inc., pic32mx320f064h Datasheet - Page 239

• Manufacturer Part Number: pic32mx320f064h
• Description: 64/100-pin General Purpose, 32-bit Flash Microcontrollers
• Manufacturer: Microchip Technology Inc.

11.6
Most of the peripherals on the device are clocked using
the PBCLK. The peripheral bus can be scaled relative
to the SYSCLK to minimize the dynamic power con-
sumed by the peripherals. The PBCLK divisor is con-
trolled by PBDIV<1:0> (OSCCON<20:19>), allowing
SYSCLK-to-PBCLK ratios of 1:1, 1:2, 1:4, and 1:8. All
peripherals using PBCLK are affected when the divisor
is changed. Peripherals such as the Interrupt Control-
ler, DMA, Bus Matrix, and Prefetch Cache are clocked
directly from SYSCLK, as a result, they are not affected
by PBCLK divisor changes.
Changing the PBCLK divisor affects:
• The CPU to peripheral access latency. The CPU
• The power consumption of the peripherals. Power
To minimize dynamic power the PB divisor should be
chosen to run the peripherals at the lowest frequency
that provides acceptable system performance. When
selecting a PBCLK divider, peripheral clock require-
ments such as baud rate accuracy should be taken into
account. For example, the UART peripheral may not be
able to achieve all baud rate values at some PBCLK
divider depending on the SYSCLK value.
© 2007 Microchip Technology Inc.
has to wait for next PBCLK edge for a read to
complete. In 1:8 mode this results in a latency of
one to seven SYSCLKs.
consumption is directly proportional to the fre-
quency at which the peripherals are clocked. The
greater the divisor, the lower the power consumed
by the peripherals.
Peripheral Bus Scaling Method
Advance Information
11.6.1
The PB
save additional power when the device is in a low activ-
ity mode. The following issues need to be taken into
account when scaling the PBCLK:
• All the peripherals clocked from PBCLK will scale
• Any communication through a peripheral on the
The following steps are recommended if the user
intends to scale the PBCLK divisor dynamically:
• Disable all communication peripherals whose
• Update the Baud Rate Generator (BRG) settings
• Change the peripheral bus ratio to the desired
• Enable all communication peripherals whose
at the same ratio, at the same time. This needs to
be accounted in peripherals which need to main-
tain a constant baud rate, or pulse period even in
low-power modes.
peripheral bus that is in progress when the
PBCLK changes may cause a data or protocol
error due to a frequency change during
transmission or reception.
baud rate will be affected. Care should be taken to
ensure that no communication is currently in
progress before disabling the peripherals as it
may result in protocol errors.
for peripherals as required for operation at the
new PBCLK frequency.
value.
baud rate were affected.
Note:
CLK
PIC32MX FAMILY
DYNAMIC PERIPHERAL BUS
SCALING METHOD
can be scaled dynamically, by software, to
Modifying the peripheral baud rate is done
by writing to the associated peripheral
SFRs. To minimize latency, the peripher-
als should be modified in the mode where
the PBCLK is running at its highest
frequency.
DS61143A-page 237