pic32mx320f064h Microchip Technology Inc., pic32mx320f064h Datasheet - Page 336

• Manufacturer Part Number: pic32mx320f064h
• Description: 64/100-pin General Purpose, 32-bit Flash Microcontrollers
• Manufacturer: Microchip Technology Inc.

PIC32MX FAMILY
17.2.4.4
This Framed SPI mode is enabled by setting bits
MSTEN (SPIxCON<5>), FRMEN (SPIxCON<31>),
and FRMSYNC (SPIxCON<30>) to ‘1’. The SSx pin is
an input, and it is sampled on the sample edge of the
SPI clock. When it is sampled active, high, or low
depending on bit FRMPOL (SPIxCON<29>), data will
be transmitted on the subsequent transmit edge of the
SPI clock, as shown in Figure 17-7. The interrupt flag
SPIxIF is set when the transmission is complete. The
user must make sure that the correct data is loaded into
the SPIxBUF for transmission before the signal is
received at the SSx pin. A connection diagram indicat-
ing signal directions for this operating mode is shown in
Figure 17-8.
The SCK and SDO pins are outputs, the SDI and SSx
pins are inputs.
(SPIxCON<12>), disables transmission at the SDO pin
if Receive Only mode of operation is desired.
Refer to Table 17-7.
The SDI pin must be configured to properly sample the
data received from the slave device by configuring the
sample bit, SMP (SPIxCON<9>).
In Master mode, the SCK clock edge and polarity must
be configured properly for the master and slave device
to correctly transfer data synchronously.
Refer to timing diagram shown in Figure 17-3 to deter-
mine the appropriate settings.
17.2.4.5
The following bits must be configured as shown for the
Master mode of operation when configuring the
SPIxCON register:
• Enable Master Mode –
• Enable Framed SPI support –
• Select SSx pin as Frame Slave (input) –
The remaining bits are shown with example configura-
tions and may be configured as desired:
• Enable module control of SDO pin –
• Configure SCK clock polarity to Idle high –
• Configure SCK clock edge transition from Idle to
• Select SSx active low pin polarity –
• Select 16-bit data width –
• Sample data input at middle – SMP
DS61143A-page 334
FRMSYNC (SPIxCON<30>) = 1
active – CKE (SPIxCON<8>) = 0
(SPIxCON<9>) = 0
MSTEN (SPIxCON<5>) = 1
FRMEN (SPIxCON<31>) = 1
DISSDO (SPIxCON<12>) = 0
CKP (SPIxCON<6>) = 1
FRMPOL (SPIxCON<29>) = 0
MODE<32,16> (SPIxCON<11:10>) = 01
SPI Master Mode and Frame Slave
Mode Operations
Master SPIxCON Configuration
Setting the control bit, DISSDO
Advance Information
• Enable SPI module when CPU Idle – SIDL
17.2.4.6
The following steps are used to set up the SPI module
for the Slave mode of operation:
1.
2.
3.
4.
5.
6.
7.
(SPIxCON<13>) = 0
Note 1: The user must turn off the SPI device
If interrupts are used, disable the SPI interrupts
in the respective IEC0/1 register.
Stop and reset the SPI module by clearing the
ON bit.
Clear the receive buffer.
If using interrupts, the following additional steps
are performed:
• Clear the SPIx interrupt flags/events in the
• Set the SPIx interrupt enable bits in the
• Write the SPIx interrupt priority and subprior-
Clear the SPIROV bit (SPIxSTAT<6>).
Write the selected configuration settings to the
SPIxCON register.
Enable SPI operation by setting the ON bit
(SPIxCON<15>).
respective IFS0/1 register.
respective IEC0/1 register.
ity bits in the respective IPC5/7 register.
2: The SPIxSR register cannot be written
3: Receiving a frame sync pulse will start a
prior to changing the CKE or CKP bits.
Otherwise, the behavior of the device is
not ensured.
into directly by the user. All writes to the
SPIxSR register are performed through
the SPIxBUF register.
transmission, regardless of whether or
not data was written to SPIxBUF. If a
write was not performed, zeros will be
transmitted.
Framed Slave Mode Initialization
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