pic32mx320f064h Microchip Technology Inc., pic32mx320f064h Datasheet - Page 345

• Manufacturer Part Number: pic32mx320f064h
• Description: 64/100-pin General Purpose, 32-bit Flash Microcontrollers
• Manufacturer: Microchip Technology Inc.

18.0
The Inter-Integrated Circuit (I
complete hardware support for both Slave and Multi-
Master modes of the I
standard. Figure 18-1 shows the I
diagram.
The PIC32MX Family devices have up to two I
face modules, denoted as I2C1 and I2C2. Each I
module has a 2-pin interface: the SCLx pin is clock and
the SDAx pin is data.
Each I
key features:
• I
• I
• I
• I
• Serial Clock Synchronization for I
• I
• Provides Support for Address Bit Masking.
18.1
The hardware fully implements all the master and slave
functions of the I
specifications, as well as 7 and 10-bit addressing.
The I
master on an I
The following types of I
• I
• I
For details about the communication sequence in each
of these modes, please refer to the “PIC32MX Family
Reference Manual” (DS61132).
© 2007 Microchip Technology Inc.
Note:
Operation.
Master and Slaves.
used as a Handshake Mechanism to Suspend
and Resume Serial Transfer (SCLREL control).
Collision and Arbitrates Accordingly.
2
2
2
2
2
2
2
C Interface Supporting both Master and Slave
C Slave Mode Supports 7 and 10-Bit Address.
C Master Mode Supports 7 and 10-Bit Address.
C Port allows Bidirectional Transfers between
C Supports Multi-master Operation; Detects Bus
C Slave Operation with 7 or 10-Bit Address
C Master Operation with 7 or 10-Bit Address
2
2
C module can operate either as a slave or a
C module ‘I2Cx’ (x = 1 or 2) offers the following
INTER-INTEGRATED CIRCUIT
(I
Operating Modes
2
Reference Manual” (DS61132) for a
This data sheet summarizes the features of
the PIC32MX family of devices. It is not
intended to be a comprehensive reference
source. Refer to the “PIC32MX Family
detailed description of this peripheral.
C™)
2
C bus.
2
C Standard and Fast mode
2
C operation are supported:
2
C serial communication
2
C) module provides
2
C Port can be
2
C module block
Advance Information
2
C inter-
2
C
18.2
The I2CxCON register allows control of the module’s
operation. The I2CxCON register is readable and writ-
able. I2CxSTAT register contains status flags indicating
the module’s state during operation.
I2CxRCV is the receive register. When the incoming
data is shifted completely, it is moved to the I2CxRCV
register. I2CxTRN is the transmit register to which
bytes are written during a transmit operation.
The I2CxADD register holds the slave address. A
Status bit, ADD10, indicates 10-Bit Addressing mode.
The I2CxBRG acts as the Baud Rate Generator (BRG)
reload value.
In receive operations, I2CxRSR and I2CxRCV together
form a double-buffered receiver. When I2CxRSR
receives a complete byte, it is transferred to I2CxRCV
and an interrupt pulse is generated. The I2CxRSR shift
register is not directly accessable to the programmer.
18.3
The I
Slave Interrupt (I2CxSIF), Master Interrupt (I2CxMIF)
and Bus Collision Interrupt (I2CxBIF).
18.4
In I
Generator (BRG) resides in the I2CxBRG register.
When the BRG is loaded with this value, the BRG
counts down to ‘0’ and stops until another reload has
taken place. If clock arbitration is taking place, for
instance, the BRG is reloaded when the SCLx pin is
sampled high.
As per the I
400 kHz. However, the user can specify any baud rate
up to 1 MHz. I2CxBRG values of ‘0’ or ‘1’ are illegal.
EQUATION 18-1:
PBCLK is the peripheral clock speed. FSCL is the
desired I
2
C Master mode, the reload value for the Baud Rate
2
C module generates three interrupt signals:
I2C
PIC32MX FAMILY
2
I
I
Baud Rate Generator
C bus speed.
2
2
C Registers
C Interrupts
x
2
BRG =
C standard, F
[
SERIAL CLOCK RATE
FSCL x 2
PBCLK
SCL
may be 100 kHz or
DS61143A-page 343
]
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