pic32mx320f064h Microchip Technology Inc., pic32mx320f064h Datasheet - Page 339

• Manufacturer Part Number: pic32mx320f064h
• Description: 64/100-pin General Purpose, 32-bit Flash Microcontrollers
• Manufacturer: Microchip Technology Inc.

FIGURE 17-9:
17.2.4.10
This Framed SPI mode is enabled by setting bits
MSTEN
(SPIxCON<31>)
(SPIxCON<30>) to ‘1’. Therefore, both the SCKx and
SSx pins will be inputs. The SSx pin will be sampled on
the sample edge of the SPI clock. When SSx is sam-
pled active, high or low depending on bit, FRMPOL
(SPIxCON<29>), data will be transmitted on the next
transmit edge of SCKx. A connection diagram indicat-
ing signal directions for this operating mode is shown in
Figure 17-10.
The SDO pins is an output and the SCK, SDI and SSx
pins are inputs. Setting the control bit, DISSDO
(SPIxCON<12>), disables transmission at the SDO pin
if Receive Only mode of operation is desired.
Refer to Table 17-7.
The SDI pin must be configured to properly sample the
data received from the slave device by configuring the
sample bit, SMP (SPIxCON<9>).
Refer to timing diagram shown in Figure 17-7 to deter-
mine the appropriate settings.
17.2.4.11
The following bits must be configured as shown for the
Slave mode of operation when configuring the
SPIxCON register:
• Enable Slave Mode –
• Enable Framed SPI support –
• Select SSx pin as Frame Slave (input) –
© 2007 Microchip Technology Inc.
MSTEN (SPIxCON<5>) = 0
FRMEN (SPIxCON<31>) = 1
FRMSYNC(SPIxCON<30>) = 1
(SPIxCON<5>)
SPI Slave Mode and Frame Slave
Mode
Slave SPIxCON Configuration
Note 1: In Framed SPI modes, the SSx pin is used to transmit/receive the frame synchronization pulse.
2: Framed SPI modes require the use of all four pins (i.e., using the SSx pin is not optional).
[SPI Slave, Frame Master]
to
SPI SLAVE, FRAME MASTER CONNECTION DIAGRAM
‘1’,
PIC32MX
to
and
‘0’,
FRMSYNC
Advance Information
SDOx
SCKx
SDIx
SSx
FRMEN
Serial Clock
Frame Sync
Pulse
(1)(2)
The remaining bits are shown with example configura-
tions and may be configured as desired:
• Enable module control of SDO pin –
• Configure SCK clock polarity to Idle high –
• Configure SCK clock edge transition from Idle to
• Select SSx active-low pin polarity – FRMPOL
• Select 16-bit data width –
• Sample data input at middle –
• Enable SPI module when CPU Idle –
DISSDO (SPIxCON<12>) = 0
CKP (SPIxCON<6>) = 1
active – CKE (SPIxCON<8>) = 0
(SPIxCON<29>) = 0
MODE<32,16> (SPIxCON<11:10>) = ‘01’
SMP (SPIxCON<9>) = 0
SIDL (SPIxCON<13>) = 0
SDOx
SDIx
SCKx
SSx
[SPI Master, Frame Slave]
PIC32MX FAMILY
PROCESSOR 2
DS61143A-page 337