pic32mx320f064h Microchip Technology Inc., pic32mx320f064h Datasheet - Page 220

• Manufacturer Part Number: pic32mx320f064h
• Description: 64/100-pin General Purpose, 32-bit Flash Microcontrollers
• Manufacturer: Microchip Technology Inc.

PIC32MX FAMILY
10.2.1.3
In order to ensure that a crystal oscillator (or ceramic
resonator) has started and stabilized, an Oscillator
Start-up Timer (OST) is provided. The OST is a simple
10-bit counter that counts 1024 T
releasing the oscillator clock to the rest of the system.
This time-out period is designated as T
tude of the oscillator signal must reach the V
thresholds for the oscillator pins before the OST can
begin to count cycles.
The T
has to restart (i.e., on POR, BOR and wake-up from
Sleep mode). The Oscillator Start-up Timer is applied to
the MS and HS modes for the primary oscillator, as well
as the secondary oscillator, see Section 10.2.1.5
“Secondary Oscillator (SOSC)”.
DS61143A-page 218
OST
interval is required every time the oscillator
Oscillator Start-up Timer
OSC
OST
cycles before
. The ampli-
Advance Information
IL
and V
IH
10.2.1.4
The system clock PLL provides a user configurable
input divider, multiplier, and output divider which can be
used with the XT, HS and EC Primary Oscillator modes
and with the Internal Fast RC Oscillator (FRC) mode to
create a variety of clock frequencies from a single clock
source.
The Input divider, multiplier, and output divider control
initial value bits are contained in the in the DEVCFG2
device Configuration register. The multiplier and output
divider bits are also contained in the OSCCON register.
As part of a device Reset, values from the device Con-
figuration register, DEVCFG2, are copied to the OSC-
CON register. This allows the user to preset the input
divider to provide the appropriate input frequency to the
PLL and set an initial PLL multiplier when programming
the device. At runtime the multiplier, divider and output
divider can be changed by software to scale the clock
frequency to suit the application. The PLL input divider
cannot be changed at run time. This is to prevent apply-
ing an input frequency outside the specified limits to the
PLL.
To configure the PLL the following steps are required:
1.
2.
3.
Combinations of PLL input divider, multiplier and output
divider provide a combined multiplier of approximately
0.006 to 24 times the input frequency. For reliable oper-
ation the output of the PLL module must not exceed the
maximum clock frequency of the device. The PLL input
divider value should be chosen to limit the input fre-
quency to the PLL to the range of 4 MHz to 5 MHz.
Due to the time required for the PLL to provide a stable
output, a Status bit SLOCK (OSCCON<5>) is provided.
When the clock input to the PLL is changed, this bit is
driven low (‘0’). After the PLL has achieved a lock or the
PLL start-up timer has expired, the bit is set. The bit will
be set upon the expiration of the timer even if the PLL
has not achieved a lock.
Calculate the PLL input divider, PLL multiplier,
and PLL output divider values.
Set the PLL input divider and the initial PLL mul-
tiplier value in the DEVCFG2 register when pro-
gramming the part.
At runtime the PLL multiplier and PLL output
divider can be changed to suit the application.
System Clock Phase Locked Loop
(PLL)
© 2007 Microchip Technology Inc.