pic32mx320f064h Microchip Technology Inc., pic32mx320f064h Datasheet - Page 405

• Manufacturer Part Number: pic32mx320f064h
• Description: 64/100-pin General Purpose, 32-bit Flash Microcontrollers
• Manufacturer: Microchip Technology Inc.

REGISTER 21-2:
© 2007 Microchip Technology Inc.
bit 31
bit 23
bit 15
bit 7
Legend:
R = Readable bit
U = Unimplemented bit
bit 31-16
bit 15
bit 14
bit 13
bit 12
ALRMEN
R/W-0
R/W-0
U-0
U-0
—
—
Unimplemented: Read as ‘0’
ALRMEN: Alarm Enable bit
1 = Alarm is enabled
0 = Alarm is disabled
Note: Hardware clears ALRMEN anytime the alarm event occurs, when ARPT<7:0> = 00 and
CHIME: Chime Enable bit
1 = Chime is enabled – ARPT<7:0> is allowed to roll over from 00 to FF
0 = Chime is disabled – ARPT<7:0> stops once it reaches 00
Note: This field should not be written when RTCCON = 1 (RTCCON<15>) and ALRMSYNC = 1.
PIV: Alarm Pulse Initial Value bit
When ALRMEN = 0, PIV is writable and determines the initial value of the alarm pulse.
When ALRMEN = 1, PIV is read-only and returns the state of the alarm pulse.
Note: This field should not be written when RTCCON = 1 (RTCCON<15>) and ALRMSYNC = 1.
ALRMSYNC: Alarm Sync bit
1 = ARPT<7:0> and ALRMEN may change as a result of a half-second rollover during a read.
0 = ARPT<7:0> and ALRMEN can be read without concerns of rollover because prescaler is
Note: This assumes a CPU read will execute in less than 32 PBCLKs.
CHIME
R/W-0
R/W-0
The ARPT must be read repeatedly until the same value is read twice. This must be done since
multiple bits may be changing, which are then synchronized to the PB clock domain.
U-0
U-0
> 32 RTC clock away from a half-second rollover
—
—
RTCALRM: RTC ALARM CONTROL REGISTER
CHIME = 0. This field should not be written when RTCCON = 1 (RTCCON<15>) and
ALRMSYNC = 1.
W = Writable bit
-n = Bit Value at POR: (‘0’, ‘1’, x = Unknown)
R/W-0
R/W-0
U-0
U-0
PIV
—
—
Advance Information
ALRMSYNC
R/W-0
U-0
U-0
R-0
—
—
ARPT<7:0>
P = Programmable bit
R/W-0
R/W-0
U-0
U-0
—
—
PIC32MX FAMILY
(1)
R/W-0
R/W-0
U-0
U-0
—
—
AMASK<3:0>
r = Reserved bit
R/W-0
R/W-0
U-0
U-0
—
—
DS61143A-page 403
R/W-0
R/W-0
U-0
U-0
—
—
bit 24
bit 16
bit 8
bit 0