pic32mx320f064h Microchip Technology Inc., pic32mx320f064h Datasheet - Page 312

• Manufacturer Part Number: pic32mx320f064h
• Description: 64/100-pin General Purpose, 32-bit Flash Microcontrollers
• Manufacturer: Microchip Technology Inc.

PIC32MX FAMILY
9.
10. Set the ON (TxCON<15>) bit to ‘1’ which enables
11. Upon the first match between TMRx and OCxR,
12. When the incrementing timer matches the Sec-
EXAMPLE 16-1:
DS61143A-page 310
//
//
//
#pragma interupt OC1IntHandler ipl4 vector 6
void CmpIntHandler(void)
{
}
Set the OCM bits to ‘100’ and the OCTSEL
(OCxCON<3>) bit to the desired timer source.
The OCx pin state will now be driven low.
the compare time base to count.
the OCx pin will be driven high.
ondary Compare register, OCxRS, the second
and trailing edge (high-to-low) of the pulse is
driven onto the OCx pin. No additional pulses are
driven onto the OCx pin and it remains at low. As
The following code example will set the Output Compare 1 module
for interrupts on the single pulse event and select Timer 2
as the clock source for the compare time base.
T2CON = 0x0010;
OC1CON = 0x0000;
OC1CON = 0x0004;
OC1R = 0x3000;
OC1RS = 0x3003;
PR2 = 0x3003;
IF0CLR = 0x00000080;
IE0SET = 0x00000080;
IPC1SET = 0x0030000;
IPC1SET = 0x00000003;
T2CONSET = 0x8000;
OC1CONSET = 0x8000;
// Example code for Output Compare 1 ISR:
// insert user code here
IFS0CLR = 0x00000080; // Clear the OC1 interrupt flag
EXAMPLE CODE
// Configure Timer 2 for a prescaler of 2
// Turn off OC1 while doing setup.
// Configure for single pulse mode
// Initialize primary Compare Register
// Initialize secondary Compare Register
// Set period (PR2 is now 32-bits wide)
// configure int
// Clear the OC1 interrupt flag
// Enable OC1 interrupt
// Set OC1 interrupt subpriority to 3,
// the highest level
// Set subpriority to 3, maximum
// Enable timer2
// Enable the OC1 module
Advance Information
13. To initiate another single pulse output, change the
a result of the second compare match event, the
OCxIF interrupt flag bit is set, which will result in
an interrupt if it is enabled, by setting the OCxIE
bit. For further information on peripheral
interrupts, refer to Section 9.0 “Interrupts”.
Timer and Compare register settings, if needed,
and then issue a write to set the OCM bits to ‘100’.
Disabling and re-enabling of the timer and clear-
ing the TMRx register are not required, but may
be advantageous for defining a pulse from a
known event time boundary.
© 2007 Microchip Technology Inc.