pic32mx320f064h Microchip Technology Inc., pic32mx320f064h Datasheet - Page 78

• Manufacturer Part Number: pic32mx320f064h
• Description: 64/100-pin General Purpose, 32-bit Flash Microcontrollers
• Manufacturer: Microchip Technology Inc.

PIC32MX FAMILY
REGISTER 5-8:
DS61143A-page 76
bit 31
bit 23
bit 15
bit 7
Legend:
R = Readable bit
U = Unimplemented bit
bit 31-24
bit 23-16
bit 15-8
bit 7
bit 6
bit 5
bit 4
CFORCE
R/W-1
R/W-1
U-0
S-0
—
Unimplemented: Read as ‘0’
CHAIRQ<7:0>: IRQ that will abort Channel Transfer bits
11111111 = Interrupt 255 will abort any transfers in progress and set CHAIF flag
• • •
00000001 = Interrupt 1 will abort any transfers in progress and set CHAIF flag
00000000 = Interrupt 0 will abort any transfers in progress and set CHAIF flag
CHSIRQ<7:0>: IRQ that will Start Channel Transfer bits
11111111 = Interrupt 255 will initiate a DMA transfer
• • •
00000001 = Interrupt 1 will initiate a DMA transfer
00000000 = Interrupt 0 will initiate a DMA transfer
CFORCE: DMA Forced Transfer bit
1 = A DMA transfer is forced to begin when this bit is written to a ‘1’
0 = This bit always reads ‘0’
CABORT: DMA Abort Transfer bit
1 = A DMA transfer is aborted when this bit is written to a ‘1’
0 = This bit always reads ‘0’
PATEN: Channel Pattern Match Abort Enable bit
1 = Abort transfer and clear CHEN on pattern match
0 = Pattern match is disabled
SIRQEN: Channel Start IRQ Enable bit
1 = Start channel cell transfer if an interrupt matching CHSIRQ occurs
0 = Interrupt number CHSIRQ is ignored and does not start a transfer
CABORT
R/W-1
R/W-1
U-0
S-0
—
DCHXECON: DMA CHANNEL X EVENT CONTROL REGISTER
W = Writable bit
-n = Bit Value at POR: (‘0’, ‘1’, x = Unknown)
PATEN
R/W-1
R/W-1
R/W-0
U-0
—
Advance Information
SIRQEN
R/W-1
R/W-1
R/W-0
U-0
CHAIRQ<7:0>
CHSIRQ<7:0>
—
AIRQEN
R/W-1
R/W-1
R/W-0
U-0
—
R/W-1
R/W-1
U-0
U-0
—
—
© 2007 Microchip Technology Inc.
R/W-1
R/W-1
U-0
U-0
—
—
R/W-1
R/W-1
U-0
U-0
—
—
bit 24
bit 16
bit 8
bit 0