pic32mx320f064h Microchip Technology Inc., pic32mx320f064h Datasheet - Page 23

• Manufacturer Part Number: pic32mx320f064h
• Description: 64/100-pin General Purpose, 32-bit Flash Microcontrollers
• Manufacturer: Microchip Technology Inc.

2.2.1
The PIC32MX core execution unit implements a load/
store architecture with single-cycle ALU operations
(logical, shift, add, subtract) and an autonomous
multiply/divide unit. The PIC32MX core contains thirty-
two 32-bit general-purpose registers used for integer
operations and address calculation. One additional
register file shadow set (containing thirty-two registers)
is added to minimize context switching overhead during
interrupt/exception
consists of two read ports and one write port and is fully
bypassed to minimize operation latency in the pipeline.
• 32-bit adder used for calculating the data address
• Address unit for calculating the next instruction
• Logic for branch determination and branch target
• Load aligner
• Bypass multiplexers used to avoid stalls when
• Leading Zero/One detect unit for implementing the
• Arithmetic Logic Unit (ALU) for performing bitwise
• Shifter & Store Aligner
© 2007 Microchip Technology Inc.
The execution unit includes:
address
address calculation
executing
producing instructions are followed closely by
consumers of their results
CLZ and CLO instructions
logical operations
EXECUTION UNIT
instructions
processing.
streams
The
where
register
Advance Information
data
file
2.2.2
The PIC32MX core includes a multiply/divide unit
(MDU) that contains a separate pipeline for multiply
and divide operations. This pipeline operates in parallel
with the integer unit (IU) pipeline and does not stall
when the IU pipeline stalls. This allows MDU
operations to be partially masked by system stalls and/
or other integer unit instructions.
The high-performance MDU consists of a 32x16 booth
recoded multiplier, result/accumulation registers (HI
and LO), a divide state machine, and the necessary
multiplexers and control logic. The first number shown
(‘32’ of 32x16) represents the rs operand. The second
number (‘16’ of 32x16) represents the rt operand. The
PIC32MX core only checks the value of the latter (rt)
operand to determine how many times the operation
must pass through the multiplier. The 16x16 and 32x16
operations pass through the multiplier once. A 32x32
operation passes through the multiplier twice.
The MDU supports execution of one 16x16 or 32x16
multiply operation every clock cycle; 32x32 multiply
operations can be issued every other clock cycle.
Appropriate interlocks are implemented to stall the
issuance of back-to-back 32x32 multiply operations.
The multiply operand size is automatically determined
by logic built into the MDU.
Divide operations are implemented with a simple 1 bit
per clock iterative algorithm. An early-in detection
checks the sign extension of the dividend (rs) operand.
If rs is 8 bits wide, 23 iterations are skipped. For a 16-
bit-wide rs, 15 iterations are skipped, and for a 24-bit-
wide rs, 7 iterations are skipped. Any attempt to issue
a subsequent MDU instruction while a divide is still
active causes an IU pipeline stall until the divide
operation is completed.
Table 2-1 lists the repeat rate (peak issue rate of cycles
until the operation can be reissued) and latency
(number of cycles until a result is available) for the
PIC32MX core multiply and divide instructions. The
approximate latency and repeat rates are listed in
terms of pipeline clocks.
MULTIPLY/DIVIDE UNIT (MDU)
PIC32MX
DS61143-page 21