pic32mx320f064h Microchip Technology Inc., pic32mx320f064h Datasheet - Page 29

• Manufacturer Part Number: pic32mx320f064h
• Description: 64/100-pin General Purpose, 32-bit Flash Microcontrollers
• Manufacturer: Microchip Technology Inc.

2.3.1
The PIC32MX core provides a simple Fixed Mapping
Translation (FMT) mechanism that is smaller and
simpler than a full Translation Lookaside Buffer (TLB)
found in other MIPS cores. Like a TLB, the FMT
performs virtual-to-physical address translation and
provides attributes for the different segments. Those
segments that are unmapped in a TLB implementation
(kseg0 and kseg1) are translated identically by the
FMT. Figure 2-3 shows how the FMT is implemented in
the PIC32MX core.
FIGURE 2-3:
In general, the FMT also determines the cacheability of
each segment. These attributes are controlled via bits
in the Config register. Table 2-4 shows the encoding for
the K23 (bits 30:28), KU (bits 27:25), and K0 (bits 2:0)
fields of the Config register. The PIC32MX core passes
these Config fields to the Prefetch Cache module to
determine cacheability of Program Memory Flash
accesses. Table 2-5 shows how the cacheability of the
virtual address segments is controlled by these fields.
TABLE 2-4:
© 2007 Microchip Technology Inc.
K23, KU, and K0
Config Register
Fields
2
3
FIXED MAPPING TRANSLATION
CACHE COHERENCY
ATTRIBUTES
ADDRESS TRANSLATION DURING MEMORY ACCESS
Cache Coherency Attribute
Instruction
Address
Calculator
Data
Address
Calculator
Uncached.
Cacheable
Virtual
Address
Virtual
Address
Advance Information
FMT
Physical
Address
Physical
Address
SRAM
Interface
Instn
SRAM
Data
SRAM
PIC32MX
DS61143-page 27