pic32mx320f064h Microchip Technology Inc., pic32mx320f064h Datasheet - Page 323

• Manufacturer Part Number: pic32mx320f064h
• Description: 64/100-pin General Purpose, 32-bit Flash Microcontrollers
• Manufacturer: Microchip Technology Inc.

REGISTER 17-1:
© 2007 Microchip Technology Inc.
bit 31
bit 23
bit 15
bit 7
Legend:
R = Readable bit
U = Unimplemented bit
bit 31
bit 30
bit 29
bit 28-18
bit 17
bit 16
bit 15
bit 14
bit 13
bit 12
FRMEN
R/W-0
R/W-0
R/W-0
SSEN
U-0
ON
—
FRMEN: Framed SPI Support bit
1 = Framed SPI support is enabled (SSx pin used as FSYNC input/output)
0 = Framed SPI support is disabled
FRMSYNC: Frame Sync Pulse Direction Control on SSx pin bit (Framed SPI mode only)
1 = Frame sync pulse input (Slave mode)
0 = Frame sync pulse output (Master mode)
FRMPOL: Frame Sync Polarity bit (Framed SPI mode only)
1 = Frame pulse is active-high
0 = Frame pulse is active-low
Unimplemented: Read as ‘0’
SPIFE: Frame Sync Pulse Edge Select bit (framed SPI mode only)
1 = Frame synchronization pulse coincides with the first bit clock
0 = Frame synchronization pulse precedes the first bit clock
Unimplemented: Read as ‘0’
ON: SPI Peripheral On bit
1 = SPI Peripheral is enabled
0 = SPI Peripheral is disabled
FRZ: Freeze in DEBUG Exception Mode bit
1 = Freeze operation when CPU enters Debug Exception mode
0 = Continue operation when CPU enters Debug Exception mode
Note: FRZ is writable in Debug Exception mode only, it is forced to ‘0’ in Normal mode.
SIDL: Stop in IDLE Mode bit
1 = Discontinue operation when CPU enters in Idle mode
0 = Continue operation in Idle mode
DISSDO: Disable SDOx pin bit
1 = SDOx pin is not used by the module. Pin is controlled by associated PORT register
0 = SDOx pin is controlled by the module
FRMSYNC
R/W-0
R/W-0
R/W-0
CKP
FRZ
U-0
—
SPIXCON: SPI CONTROL REGISTER
W = Writable bit
-n = Bit Value at POR: (‘0’, ‘1’, x = Unknown)
FRMPOL
MSTEN
R/W-0
R/W-0
R/W-0
SIDL
U-0
—
Advance Information
DISSDO
R/W-0
U-0
U-0
U-0
—
—
—
P = Programmable bit
MODE32
R/W-0
U-0
U-0
U-0
—
—
—
PIC32MX FAMILY
MODE16
R/W-0
U-0
U-0
U-0
—
—
—
r = Reserved bit
R/W-0
SPIFE
R/W-0
SMP
U-0
U-0
—
—
DS61143A-page 321
R/W-0
CKE
U-0
U-0
U-0
—
—
—
bit 24
bit 16
bit 8
bit 0