pic32mx320f064h Microchip Technology Inc., pic32mx320f064h Datasheet - Page 196

• Manufacturer Part Number: pic32mx320f064h
• Description: 64/100-pin General Purpose, 32-bit Flash Microcontrollers
• Manufacturer: Microchip Technology Inc.

PIC32MX FAMILY
9.5
9.5.1
The user is able to assign a group priority to each of the
interrupt vectors. The groups’ priority level bits are
located in the IPCx register. Each IPCx register con-
tains group priority bits for four interrupt vectors. The
user-selectable priority levels range from 1 (the lowest
priority) to 7 (the highest). If an interrupt priority is set to
zero, the interrupt vector is disabled for both interrupt
and wake-up purposes. Interrupt vectors with a higher
priority level preempt lower priority interrupts. The user
must move the Requested Interrupt Priority bit of the
EXAMPLE 9-3:
9.5.2
The user can assign a subpriority level within each
group priority. The subpriority will not cause preemption
of an interrupt in the same priority; rather, if two inter-
rupts with the same priority are pending, the interrupt
with the highest subpriority will be handled first. The
subpriority bits are located in the IPCx register. Each
EXAMPLE 9-4:
DS61143A-page 194
/*
The following code example will set the subpriority to level 2.
must be performed (See Example 9-2)
*/
IPC0CLR = 0x00000003;
IPC0SET = 0x00000002;
/*
The following code example will set the priority to level 2.
must be performed (See Example 9-2)
*/
IPC0CLR = 0x0000001C;
IPC0SET = 0x00000008;
Interrupt Priorities
INTERRUPT GROUP PRIORITY
INTERRUPT SUBPRIORITY
SETTING GROUP PRIORITY LEVEL
SETTING SUBPRIORITY LEVEL
Advance Information
// clear the subpriority level
// set the subpriority to 2
// clear the priority level
// set priority level to 2
Cause register, RIPLx (Cause<15:10>), into the Status
register’s Interrupt Priority bits, IPLx (Status<15:10>),
before re-enabling interrupts. (The Cause and Status
registers are located in the CPU; refer to Section 2.0 of
this manual for more information.) This action will dis-
able all lower priority interrupts until the completion of
the Interrupt Service Routine.
IPCx register contains subpriority bits for four of the
interrupt vectors. These bits define the subpriority
within the priority level of the vector. The user-
selectable subpriority levels range from 0 (the lowest
subpriority) to 3 (the highest).
Note:
The Interrupt Service Routine (ISR) must
clear the associated interrupt flag in the
IFSx register before lowering the interrupt
priority level to avoid recursive interrupts.
Multi-Vector initialization
Multi-Vector initialization
© 2007 Microchip Technology Inc.