pic32mx320f064h Microchip Technology Inc., pic32mx320f064h Datasheet - Page 58

• Manufacturer Part Number: pic32mx320f064h
• Description: 64/100-pin General Purpose, 32-bit Flash Microcontrollers
• Manufacturer: Microchip Technology Inc.

PIC32MX FAMILY
4.3.2
Application code can direct the prefetch module to pre-
form a preload of a cache line and lock it with instruc-
tions or data from the flash. The Preload function uses
the CHEACC.CHEIDX register field to select the
cache line into which the load is directed. Setting
CHEACC.CHEWEN to a ‘1’ enables writes to the
CHETAG register.
Writing
CHETAG.LLOCK = 1 causes a preload request to the
prefetch module. The controller acknowledges the
request in the cycle after the write and if possible stops
any outstanding flash access and stalls any CPU load
from the cache or Flash.
When it has finished or stalled the previous transac-
tion, it initiates a flash read to fetch the instructions or
data requested using the address in CHETAG.LTAG.
After the programmed number of wait states as
defined by CHECON.PFMWS, the controller updates
the data array with the values read from flash. On the
update it sets CHETAG.LVALID = 1. The LRU state of
the line is not affected.
Once the controller finishes updating the cache, it
allows CPU requests to complete. If this request
misses the cache, the controller initiates a flash read
which incurs the full flash access time.
EXAMPLE 4-3:
DS61143A-page 56
#define INT_LINE_NUM 10
CHETAG = (ltagboot<<31) | (tmp & 0x0007fff0) | 6; // locked and invalid
CHEMSK = 0xe0; // first 4 instructions of intbase() replicated 8 times on 32-byte boundaries
CHEACC = (1<<31) | INT_LINE_NUM;
tmp = (unsigned long)intbase;
ltagboot = (tmp & 0x00c00000) ? 0 : 1; // 0x9fc????? or 0x9d0?????
PRELOAD BEHAVIOR
CHETAG.LVALID = 0
EXAMPLE CODE: DUPLICATION OF CODE USING MASK REGISTERS
Advance Information
and
4.3.3
Cache lines 10 and 11 allow masking of the CPU
address and tag address to force a match on corre-
sponding bits. The CHEMSK.LMASK field is set up to
compliment the interrupt vector spacing field in the
CPU. This feature allows boot code to lock the first
four instruction of a vector in the cache. If all vectors
contain identical instructions in their first four locations,
then setting the CHEMSK.LMASK to match the vector
spacing and the LTAG to match the vector base
address causes all the vector addresses to hit the
cache. The prefetch module responds with zero wait
states and immediately initiates a fetch of the next set
of four instruction for the requesting vector if prefetch
is enabled.
Using CHEMSK.LMASK is restricted to aligned
address ranges. Its size allows for a max range of
32KB and a minimum spacing of 32B. Using the two
lines, in conjunction provides the ability to have differ-
ent ranges and different spacing.
Setting up the address mask such that more than one
line will match an address causes undefined results.
Therefore, it is highly recommended to set up masking
before entering cacheable code.
ADDRESS MASK
© 2007 Microchip Technology Inc.