pic32mx320f064h Microchip Technology Inc., pic32mx320f064h Datasheet - Page 348

• Manufacturer Part Number: pic32mx320f064h
• Description: 64/100-pin General Purpose, 32-bit Flash Microcontrollers
• Manufacturer: Microchip Technology Inc.

PIC32MX FAMILY
18.11 Slope Control
The I
and SCLx signals for Fast mode (400 kHz). The control
bit, DISSLW, enables the user to disable slew rate
control if desired. It is necessary to disable the slew
rate control for 1 MHz mode.
18.12 Clock Arbitration
Clock arbitration occurs when the master deasserts the
SCLx pin (SCLx allowed to go high by external pull-up
resistors) during any receive, transmit or Restart/Stop
condition. When the SCLx pin is allowed to float high,
the Baud Rate Generator (BRG) is suspended from
counting until the SCLx pin is actually sampled high.
When the SCLx pin is sampled high, the Baud Rate
Generator is reloaded with the contents of I2CxBRG
and begins counting. This ensures that the SCLx high
time will always be at least one BRG rollover count in
the event that the clock is held low by an external
device.
FIGURE 18-2:
DS61143A-page 346
2
C standard requires slope control on the SDAx
TYPICAL I
PIC32MX
2
C™ INTERCONNECTION BLOCK DIAGRAM
SDA
SCL
X
X
Advance Information
V
DD
V
DD
4.7 kΩ
(typical)
18.13 Multi-Master Communication, Bus
Multi-Master mode support is achieved by bus
arbitration. When the master outputs address/data bits
onto the SDAx pin, arbitration takes place when the
master outputs a ‘1’ on SDAx by letting SDAx float high
while another master asserts a ‘0’. When the SCLx pin
floats high, data should be stable. If the expected data
on SDAx is a ‘1’ and the data sampled on the
SDAx pin = 0, then a bus collision has taken place. The
master will set the I
reset the master portion of the I
Collision and Bus Arbitration
SCL
SDA
24LC256
2
C master events interrupt flag and
© 2007 Microchip Technology Inc.
2
C port to its Idle state.