pic32mx320f064h Microchip Technology Inc., pic32mx320f064h Datasheet - Page 25

• Manufacturer Part Number: pic32mx320f064h
• Description: 64/100-pin General Purpose, 32-bit Flash Microcontrollers
• Manufacturer: Microchip Technology Inc.

2.2.3
In the MIPS architecture, CP0 is responsible for the
virtual-to-physical address translation, the exception
control system, the processor’s diagnostics capability,
the operating modes (kernel, user, and debug), and
whether
Configuration information, such as presence of options
like MIPS16e, is also available by accessing the CP0
registers, listed in Table 2-2.
TABLE 2-2:
© 2007 Microchip Technology Inc.
Note 1:
Register
Number
17-22
25-29
0-6
10
11
12
12
12
12
13
14
15
15
16
16
16
16
23
24
30
31
7
8
9
2:
interrupts
Registers used in exception processing.
Registers used during debug.
SYSTEM CONTROL
COPROCESSOR (CP0)
Register
Name
Reserved
HWREna
BadVAddr
Count
Reserved
Compare
Status
IntCtl
SRSCtl
SRSMap
Cause
EPC
PRId
EBASE
Config
Config1
Config2
Config3
Reserved
Debug
DEPC
Reserved
ErrorEPC
DESAVE
(1)
(1)
(1)
COPROCESSOR 0 REGISTERS
(1)
(2)
(1)
(2)
(1)
(2)
(1)
(1)
(1)
(1)
are
enabled
Function
Reserved in the PIC32MX core
Enables access via the RDHWR instruction to selected hardware registers
Reports the address for the most recent address-related exception
Processor cycle count
Reserved in the PIC32MX core
Timer interrupt control
Processor status and control
Interrupt system status and control
Shadow register set status and control
Provides mapping from vectored interrupt to a shadow set
Cause of last general exception
Program counter at last exception
Processor identification and revision
Exception vector base register
Configuration register
Configuration register 1
Configuration register 2
Configuration register 3
Reserved in the PIC32MX core
Debug control and exception status
Program counter at last debug exception.
Reserved in the PIC32MX core.
Program counter at last error.
Debug handler scratchpad register.
or
Advance Information
disabled.
PIC32MX
DS61143-page 23