pic32mx320f064h Microchip Technology Inc., pic32mx320f064h Datasheet - Page 292

• Manufacturer Part Number: pic32mx320f064h
• Description: 64/100-pin General Purpose, 32-bit Flash Microcontrollers
• Manufacturer: Microchip Technology Inc.

PIC32MX FAMILY
14.4
A timer can generate an interrupt on a period match
event or a gate event, caused by the falling edge of the
external gate signal.
A timer sets its corresponding interrupt flag bit, TxIF,
whenever the timer event is generated. Refer to a
specific timer mode for details regarding these event
conditions. When a timer event is generated, the inter-
rupt flag bit is set within 1 PBCLK + 2 SYSCLK cycles.
If the timer interrupt enable bit is set, TxIE = 1, an
interrupt is generated.
EXAMPLE 14-7:
EXAMPLE 14-8:
DS61143A-page 290
T4CON = 0x0;
T5CON = 0x0;
T4CONSET = 0x0038;
TMR4= 0x0;
PR4 = 0xFFFFFFFF;
IPC5SET = 0x00000004; // Set priority level=1 and
IPC5SET = 0x00000001; // Set subpriority level=1
IFS0CLR = 0x10000000; // Clear the Timer5 interrupt status flag
IEC0SET = 0x10000000; // Enable Timer5 interrupts
T4CONSET = 0x8000;
T2CON = 0x0;
TMR2 = 0x0;
PR2 = 0xFFFF;
IPC2SET = 0x0000000C; // Set priority level=3
IPC2SET = 0x00000001; // Set subpriority level=1
IFS0CLR = 0x00000100; // Clear Timer interrupt status flag
IEC0SET = 0x00000100; // Enable Timer interrupts
T2CONSET = 0x8000;
Timer Interrupts
16-BIT TIMER INTERRUPT AND PRIORITIES
32-BIT TIMER INTERRUPT AND PRIORITIES
// Stop 16-bit Timer4 and clear control register
// Stop 16-bit Timer5 and clear control register
// Enable 32-bit mode, prescaler at 1:8,
// internal clock source
// Clear contents of the TMR4 and TMR5
// registers in one 32-bit load operation
// Load PR4 and PR5 registers with 32-bit value
// 0xFFFFFFFF in one 32-bit load operation
// Could have also done this in single
// operation by assigning IPC5SET = 0x00000005
// Start Timer
// prescaler at 1:1,internal clock source
// Clear timer register
// Load period register
// Could have also done this in single
// operation by assigning IPC2SET = 0x0000000D
// Start Timer
// Stop Timer and clear control register,
Advance Information
The timer module is enabled as a source of interrupts
via the respective Timer Interrupt Enable bit, TxIE
(IECx<n>). The Timer Interrupt Flag, TxIF (IFSx<n>),
must be cleared in software.
The interrupt priority level bits and interrupt subpriority
level bits must be also be configured:
• TxIP<2:0> (IPCx<4:2>)
• TxIS<1:0> (IPCx<1:0)
Setting the timer’s interrupt priority level = 0 effectively
disables the timer’s ability to generate an interrupt.
In addition to enabling the timer interrupt, an Interrupt
Service Routine, ISR, is required. Example 14-7
through Example 14-9 show a partial code example of
an ISR.
© 2007 Microchip Technology Inc.