pic32mx320f064h Microchip Technology Inc., pic32mx320f064h Datasheet - Page 338

• Manufacturer Part Number: pic32mx320f064h
• Description: 64/100-pin General Purpose, 32-bit Flash Microcontrollers
• Manufacturer: Microchip Technology Inc.

PIC32MX FAMILY
17.2.4.7
This Framed SPI mode is enabled by setting bit
MSTEN
(SPIxCON<31>)
(SPIxCON<30>) to ‘0’. The input SPI clock will be con-
tinuous in Slave mode. The SSx pin will be an output
when bit FRMSYNC is low. Therefore, when SPIBUF is
written, the module will drive the SSx pin active, high or
low depending on bit FRMPOL (SPIxCON<29>), on the
next transmit edge of the SPI clock. The SSx pin will be
driven active for one SPI clock cycle. Data transmission
will start on the next SPI clock transmit edge. A
connection diagram indicating signal directions for this
operating mode is shown in Figure 17-9.
The SDO and SSx pins are outputs and the SCK and
SDI pins are inputs. Setting the control bit, DISSDO
(SPIxCON<12>), disables transmission at the SDO pin
if Receive Only mode of operation is desired.
Refer to Table 17-7.
The SDI pin must be configured to properly sample the
data received from the slave device by configuring the
sample bit, SMP (SPIxCON<9>).
Refer to timing diagram shown in Figure 17-6 to
determine the appropriate settings.
17.2.4.8
The following bits must be configured as shown for the
Slave mode of operation when configuring the
SPIxCON register:
• Enable Slave Mode – MSTEN (SPIxCON<5>) = 1
• Enable Framed SPI support – FRMEN
• Select SSx pin as Frame Master (output) –
The remaining bits are shown with example configura-
tions and may be configured as desired:
• Enable module control of SDO pin – DISSDO
• Configure SCK clock polarity to Idle high – CKP
• Configure SCK clock edge transition from Idle to
• Select SSx active low pin polarity – FRMPOL
• Select 16-bit data width – MODE<32,16>
• Sample data input at middle – SMP
• Enable SPI module when CPU Idle – SIDL
DS61143A-page 336
(SPIxCON<31>) = 1
(SPIxCON<12>) = 0
(SPIxCON<6>) = 1
active – CKE (SPIxCON<8>) = 0
(SPIxCON<29>) = 0
(SPIxCON<11:10>) = 01
(SPIxCON<9>) = 0
(SPIxCON<13>) = 0
FRMSYNC(SPIxCON<30>) = 0
(SPIxCON<5>)
SPI Slave Mode and Frame Master
Mode
Slave SPIxCON Configuration
to
‘1’
to
and
‘0’,
bit
bit
FRMSYNC
Advance Information
FRMEN
17.2.4.9
The following steps are used to set up the SPI module
for the Slave mode of operation:
1.
2.
3.
4.
5.
6.
7.
8.
Note 1: The user must turn off the SPI device
If interrupts are used, disable the SPI interrupts
in the respective IEC0/1 register.
Stop and reset the SPI module by clearing the
ON bit.
Clear the receive buffer.
If using interrupts, the following additional steps
are performed:
• Clear the SPIx interrupt flags/events in the
• Set the SPIx interrupt enable bits in the
• Write the SPIx interrupt prioity and subpriority
Clear the SPIROV bit (SPIxSTAT<6>).
Write the selected configuration settings to the
SPIxCON register.
Enable SPI operation by setting the ON bit
(SPIxCON<15>).
Transmission (and reception) will start as soon
as the master provides the serial clock.
respective IFS0/1 register.
respective IEC0/1 register.
bits in the respective IPC5/7 register.
2: The SPIxSR register cannot be written
prior to changing the CKE or CKP bits.
Otherwise, the behavior of the device is
not ensured.
into directly by the user. All writes to the
SPIxSR register are performed through
the SPIxBUF register.
Framed Master Mode Initialization
© 2007 Microchip Technology Inc.