pic32mx320f064h Microchip Technology Inc., pic32mx320f064h Datasheet - Page 21

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pic32mx320f064h

Manufacturer Part Number
pic32mx320f064h
Description
64/100-pin General Purpose, 32-bit Flash Microcontrollers
Manufacturer
Microchip Technology Inc.
Datasheet

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2.0
The MCU module is the heart of the PIC32MX proces-
sor.
instruction, fetches source operands, executes each
instruction, and writes the results of instruction execu-
tion to the proper destinations.
2.1
• 5-stage pipeline
• 32-bit Address and Data Paths
• MIPS32 Enhanced Architecture (Release 2)
• MIPS16e™ Code Compression
© 2007 Microchip Technology Inc.
Note:
- Multiply-Accumulate and Multiply-Subtract
- Targeted Multiply Instruction
- Zero/One Detect Instructions
- Wait Instruction
- Conditional Move Instructions (MOVN, MOVZ)
- Vectored interrupts
- Programmable exception vector base
- Atomic interrupt enable/disable
- GPR shadow registers to minimize latency
- Bit field manipulation instructions
- 16 bit encodings of 32 bit instructions to
- Special PC-relative instructions for efficient
- SAVE & RESTORE macro instructions for
- Improved support for handling 8 and 16 bit
Instructions
for interrupt handlers
improve code density
loading of addresses and constants
setting up and tearing down stack frames
within subroutines
data types
The MCU fetches instructions, decodes each
PIC32MX MCU
Features
description of this peripheral.
This data sheet summarizes the features of
the PIC32MX of devices. It is not intended
to be a comprehensive reference source.
Refer to the “PIC32MX Family Reference
Manual”
(DS61132)
for
a
Advance Information
detailed
• Simple Fixed Mapping Translation (FMT)
• Simple Dual Bus Interface
• Autonomous Multiply/Divide Unit
• Power Control
• EJTAG Debug and Instruction Trace
mechanism
- Independent 32-bit address and data busses
- Transactions can be aborted to improve
- Maximum issue rate of one 32x16 multiply
- Maximum issue rate of one 32x32 multiply
- Early-in iterative divide. Minimum 11 and
- Minimum frequency: 0 MHz
- Low-Power mode (triggered by WAIT
- Extensive use of local gated clocks
- Support for single stepping
- Virtual instruction and data address/value
- PC tracing w/ trace compression
interrupt latency
per clock
every other clock
maximum 34 clock latency (dividend (rs) sign
extension-dependent)
instruction)
breakpoints
PIC32MX
DS61143-page 19

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