pic32mx320f064h Microchip Technology Inc., pic32mx320f064h Datasheet - Page 24

• Manufacturer Part Number: pic32mx320f064h
• Description: 64/100-pin General Purpose, 32-bit Flash Microcontrollers
• Manufacturer: Microchip Technology Inc.

PIC32MX
TABLE 2-1:
The MIPS architecture defines that the result of a
multiply or divide operation be placed in the HI and LO
registers. Using the Move-From-HI (MFHI) and Move-
From-LO (MFLO) instructions, these values can be
transferred to the general-purpose register file.
In addition to the HI/LO targeted operations, the
MIPS32 architecture also defines a multiply instruction,
MUL, which places the least significant results in the
primary register file instead of the HI/LO register pair.
By avoiding the explicit MFLO instruction, required
when using the LO register, and by supporting multiple
destination
multiply-intensive operations is increased.
Two other instructions, multiply-add (MADD) and
multiply-subtract (MSUB), are used to perform the
multiply-accumulate and multiply-subtract operations.
The MADD instruction multiplies two numbers and then
adds the product to the current contents of the HI and
LO registers. Similarly, the MSUB instruction multiplies
two operands and then subtracts the product from the
HI and LO registers. The MADD and MSUB operations
are commonly used in DSP algorithms.
DS61143-page 22
MULT/MULTU, MADD/MADDU,
MSUB/MSUBU
DIV/DIVU
Opcode
registers,
MUL
LATENCIES AND REPEAT RATES
PIC32MX CORE HIGH-PERFORMANCE INTEGER MULTIPLY/DIVIDE UNIT
the
throughput
Operand Size (mul rt) (div rs)
Advance Information
of
16 bits
32 bits
16 bits
32 bits
16 bits
24 bits
32 bits
8 bits
Latency
12
19
26
33
1
2
2
3
© 2007 Microchip Technology Inc.
Repeat Rate
11
18
25
32
1
2
1
2